ZL50018 ZARLINK [Zarlink Semiconductor Inc], ZL50018 Datasheet - Page 53

• Manufacturer Part Number: ZL50018
• Description: 2 K Digital Switch with Enhanced Stratum 3 DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

004F
0050
0051
0052
0053
0054
0055
0056
0057
0058
0059
005A
005B
005C
005D
005E
005F
0060
0061
0062
0063
0064
0065
0066
0067
0068
0069
006A
006B
006C
0100
011F
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R Only
R/W
R/W
R Only
R/W
R Only
R/W
R/W
Multi-period Near Upper Limit Register - Upper 16 Bits
Multi-period Far Upper Limit Register - Lower 16 Bits
Multi-period Far Upper Limit Register - Upper 16 Bits
Multi-period Near Lower Limit Register - Lower 16 Bits
Multi-period Near Lower Limit Register - Upper 16 Bits
Multi-period Far Lower Limit Register - Lower 16 Bits
Multi-period Far Lower Limit Register - Upper 16 Bits
Reference 0 Multi-period Count Register - Lower 16 Bits
Reference 0 Multi-period Count Register - Upper 16 Bits
Reference 0 Upper Limit Register
Reference 0 Lower Limit Register
Reference 1 Multi-period Count Register - Lower 16 Bits
Reference 1 Multi-period Count Register - Upper 16 Bits
Reference 1 Upper Limit Register
Reference 1 Lower Limit Register
Reference 2 Multi-period Count Register - Lower 16 Bits
Reference 2 Multi-period Count Register - Upper 16 Bits
Reference 2 Upper Limit Register
Reference 2 Lower Limit Register
Reference 3 Multi-period Count Register - Lower 16 Bits
Reference 3 Multi-period Count Register - Upper 16 Bits
Reference 3 Upper Limit Register
Reference 3 Lower Limit Register
Interrupt Register
Interrupt Mask Register
Interrupt Clear Register
Reference Status Register
Reference Mask Register
Reference Frequency Status Register
Output Jitter Control Register
Stream Input Control Registers 0 - 31
Table 17 - Address Map for Registers (A13 = 0) (continued)
Zarlink Semiconductor Inc.
ZL50018
53
MPNULRU
MPFULRL
MPFULRU
MPNLLRL
MPNLLRU
MPFLLRL
MPFLLRU
R0MPCRL
R0MPCRU
R0ULR
R0LLR
R1MPCRL
R1MPCRU
R1ULR
R1LLR
R2MPCRL
R2MPCRU
R2ULR
R2LLR
R3MPCRL
R3MPCRU
R3ULR
R3LLR
IR
IMR
ICR
RSR
RMR
RFSR
OJCR
SICR0 - 31
DPLL/Hardware
DPLL/Hardware
DPLL/Hardware
DPLL/Hardware
DPLL/Hardware
DPLL/Hardware
DPLL/Hardware
DPLL/Hardware
DPLL/Hardware
DPLL/Hardware
DPLL/Hardware
DPLL/Hardware
DPLL/Hardware
DPLL/Hardware
DPLL/Hardware
DPLL/Hardware
DPLL/Hardware
DPLL/Hardware
DPLL/Hardware
DPLL/Hardware
DPLL/Hardware
DPLL/Hardware
DPLL/Hardware
DPLL/Hardware
DPLL/Hardware
DPLL/Hardware
DPLL/Hardware
DPLL/Hardware
DPLL/Hardware
Switch/Hardware
DPLL/Hardware
Data Sheet