ZL50018 ZARLINK [Zarlink Semiconductor Inc], ZL50018 Datasheet - Page 82

• Manufacturer Part Number: ZL50018
• Description: 2 K Digital Switch with Enhanced Stratum 3 DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Note 1:
Note 2:
15 - 0
MC[n]
Bit
External Read/Write Addresses: 0056
Reset Value: 387F
15
15
The default value represents lower bits of multi-period count for 8kHz input frequency, calculated to have 10 seconds
observation time.
When the MRLE bit of DPLLCR register is low, these registers are ignored. Depending on reference frequency (detected or
programmed through the Reference Frequency Register), the following values are used instead:
’h387F - if reference frequency is 8 kHz
’h987F - if reference frequency is 1.544 MHz
’h7FFF - if reference frequency is 2.048 MHz
’hFFFF - if reference frequency is 4.096 MHz, 8.192 MHz or 16.384 MHz
’h4EFF - if reference frequency is 19.44 MHz
MC[n]
MC[n]15 - 0
14
14
(n = 0 - 3)
Table 50 - Multi-period Count Register - Lower 16 Bits (RnMPCRL) Bits, (n = 0 - 3)
Name
MC[n]
13
13
H
(see Note 1)
MC[n]
12
12
Reference n Multi-period Count Bits: Total binary value of these bits and the
RnMPCRU register bits defines the number of reference clock periods to be measured
for the multi-period frequency check for the REFn input monitoring, minus 1.
MC[n]
11
11
H
, 005A
MC[n]
10
10
H
, 005E
MC[n]
H
Zarlink Semiconductor Inc.
9
9
, 0062
ZL50018
MC[n]
H
8
8
82
MC[n]
7
7
Description
MC[n]
6
6
MC[n]
5
5
MC[n]
4
4
MC[n]
3
3
MC[n]
2
2
Data Sheet
MC[n]
1
1
MC[n]
0
0