ZL50018 ZARLINK [Zarlink Semiconductor Inc], ZL50018 Datasheet - Page 83

• Manufacturer Part Number: ZL50018
• Description: 2 K Digital Switch with Enhanced Stratum 3 DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Note 1:
Note 2:
15 - 0
MC[n]
External Read/Write Addresses: 0057
Bit
Reset Value: 0001
15
31
MC[n]
The default value represents lower bits of multi-period count for 8 kHz input frequency, calculated to have 10 seconds
observation time.
or programmed through the Reference Frequency Register), the following values are used instead:
’h0001 - if reference frequency is 8 kHz
’h00EB - if reference frequency is 1.544 MHz
’h0138 - if reference frequency is 2.048 MHz
’h0270 - if reference frequency is 4.096 MHz
’h04E1 - if reference frequency is 8.192 MHz
’h09C3 - if reference frequency is 16.384 MHz
’h0B96 - if reference frequency is 19.44 MHz
When the MRLE bit of DPLLCR register is low, these registers are ignored. Depending on reference frequency (detected
14
30
MC[n]31 - 16
Table 51 - Multi-period Count Register - Upper 16 Bits (RnMPCRU) Bits, (n = 0 - 3)
(n = 0 - 3)
Name
MC[n]
13
29
H
(see Note 1)
MC[n]
12
28
Reference n Multi-period Count Bits: Total binary value of these bits and the
RnMPCRL register bits defines the number of reference clock periods to be measured
for the multi-period frequency check for the REFn input monitoring, minus 1.
MC[n]
11
27
H
, 005B
MC[n]
10
26
H
, 005F
MC[n]
25
H
9
Zarlink Semiconductor Inc.
, 0063
ZL50018
MC[n]
H
24
8
83
MC[n]
23
7
Description
MC[n]
22
6
MC[n]
21
5
MC[n]
20
4
MC[n]
19
3
MC[n]
18
2
Data Sheet
MC[n]
17
1
MC[n]
16
0