ZL50018 ZARLINK [Zarlink Semiconductor Inc], ZL50018 Datasheet - Page 65

• Manufacturer Part Number: ZL50018
• Description: 2 K Digital Switch with Enhanced Stratum 3 DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Note: [n] denotes input stream from 16 - 31.
Reset Value: 0000
External Read/Write Address: 0040
15 - 0
15-8
15
0
Bit
Bit
External Read Address: 00014
Reset Value: 0000
7
6
5
BER
L31
15
14
0
LIN_RES
SM_FST
Unused
Unused
Name
BERL[n]
BER
L30
Name
14
H
13
0
H
Table 28 - BER Receiver Lock Register 1 (BERLR1) Bits - Read Only
BER
L29
13
12
0
Reserved. In normal functional mode, these bits MUST be set to zero.
Linear Response of DPLL Phase Multiplier. When this bit is high, linear phase
multiplication will be used to determine the jitter transfer characteristics. (Follow the jitter
transfer as per BWCR register for small and large jitter amplitude).
When this bit is low, non-linear phase multiplication will be used to determine the jitter
transfer characteristics. (Only high jitter amplitudes follow the jitter transfer as per BWCR
register).
When 0, DPLL has better holdover stability and output jitter.
Semi-Fast Locking Control Bit. When this bit is high, the semi-fast locking mode is
enabled, allowing the Fast Frequency Lock (FFL3 - 0) bits in the BWCR register to be
used even if the DPLL slew rate limiter is not bypassed.
When this bit is low, the FFL3 - 0 bits in the BWCR register are ignored if the Bypass
Limiter bit (BLM) in the BWCR register is not set.
Reserved. In normal functional mode, this bit MUST be set to zero.
BER Receiver Lock[n]
If BERL[n] is high, it indicates that BER Receiver of STi[n] is locked.
If BERL[n] is low, it indicates that BER Receiver of STi[n] is not locked.
BER
L28
12
H
H
11
Table 29 - DPLL Control Register (DPLLCR) Bits
0
BER
L27
11
10
0
BER
L26
10
9
0
Zarlink Semiconductor Inc.
BER
L25
9
ZL50018
8
0
BER
L24
8
65
LIN_
RES
7
BER
L23
7
Description
Description
SM_
FST
6
BER
L22
6
BER
L21
5
0
5
SWF
BER
L20
4
4
BER
L19
SWE
3
3
BER
L18
2
MRLE
2
BER
L17
1
RFRE
Data Sheet
1
BER
L16
0
DPLL
_IRM
0