ZL50018 ZARLINK [Zarlink Semiconductor Inc], ZL50018 Datasheet - Page 46

• Manufacturer Part Number: ZL50018
• Description: 2 K Digital Switch with Enhanced Stratum 3 DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

15.7
To monitor reference failure based on frequency offset, multi period checking is performed. Reference validation
time is prescribed by Telcordia GR-1244-CORE and is between 10 and 30 seconds. To meet the criteria for
reference validation time, the time base for multi period monitoring has to be big enough and is programmable. To
implement hysteresis, the upper limits are split into near upper and far upper limits and the lower limits are split into
near lower and far lower limits. The reference failure is detectable only when the reference passes far limits, but
passing is not detected until the reference is within near limits. The zone between near and far limits, called the
“grey zone”, is required by standards and prevents unnecessary reference switching when the selected reference is
close to the boundary of failure.
The monitor makes a decision about reference validity after two consecutive measurements with respect to its time
base. The time base for multi-period monitoring, by default, is 10 seconds. The time base is defined in the number
of reference clock cycles and is programmable.
Assuming that the evaluation time is chosen to be the same regardless of reference frequency (10 seconds), the
parameters that allow hysteresis functionality also have the same values, regardless of the reference frequency.
These parameters (near lower, far lower, near upper and far upper limits) are programmable.
Registers containing the multi period count are: Reference Multi-Period Counter Registers: R0MPCRL, R0MPCRU,
R1MPCRL, R1MPCRU, R2MPCRL, R2MPCRU, R3MPCRL and R3MPCRU.
For the measurement length of multiple clock periods, the period count is set by the Reference Multi-Period Count
Registers - Lower 16 Bits: R0MPCRL, R1MPCRL, R2MPCRL and R3MPCRL and the Reference Multi-Period
Count Registers - Upper 16 Bits: R0MPCRU, R1MPCRU, R2MPCRU, and R3MPCRU.
The near upper measurement limits are set by the Multi-Period Near Upper Limit Registers, MPNULRL and
MPNULRU.
The far upper measurement limits are set by the Multi-Period Far Upper Limit Registers, MPFULRL and
MPFULRU.
The near lower measurement limits are set by the Multi-Period Near Lower Limit Registers, MPNLLRL and
MPNLLRU.
The far lower measurement limits are set by the Multi-Period Far Lower Limit Registers, MPFLLRL and MPFLLRU.
The registers’ default values upon the device reset comply to Stratum 3 when reference frequencies are 8 kHz. If
MRLE (bit 2) of the DPLL Control Register (DPLLCR) is not set, all above mentioned registers for limits and counter
values will be ignored and the Stratum 3 default values will be used. The values that comply to Stratum 3 for each
Multiple Period Reference Monitoring
16.384 MHz
Frequency
Reference
1.544 MHz
2.048 MHz
4.096 MHz
8.192 MHz
19.44 MHz
8 kHz
Upper Limit (in
Table 12 - Default Values for Single Period Limits
10 ns units)
‘h2E4A
‘h002B
‘h0025
‘h0007
‘h0002
‘h0011
‘h0002
Zarlink Semiconductor Inc.
Lower Limit (in
ZL50018
10 ns units)
‘h335C
‘h0055
‘h003B
‘h001E
‘h000F
‘h0008
‘h0007
46
6.4 us (10 UIp-p of 1.544 MHz)
Comment
0.3 UIp-p
0.2 UIp-p
0.2 UIp-p
0.2 UIp-p
0.2 UIp-p
0.2 UIp-p
Data Sheet