ZL50018 ZARLINK [Zarlink Semiconductor Inc], ZL50018 Datasheet - Page 101

• Manufacturer Part Number: ZL50018
• Description: 2 K Digital Switch with Enhanced Stratum 3 DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

24.2
When the CMM bit (bit 0) in the connection memory low is zero, the per-channel transmission is set to the normal
channel-switching. The connection memory low bit assignment for the channel transmission mode is shown in
Table 69 on page 101.
Connection Memory Low (CM_L) Bit Assignment
Note: For proper
13 - 9
8 - 1
Bit
15
14
15
UA
EN
0
Table 69 - Connection Memory Low (CM_L) Bit Assignment when CMM = 0
V/C
14
SCA7 - 0
CMM = 0
SSA4 - 0
Name
UAEN
V/C
SSA
µ-
13
4
law/A-law conversion, the CM_H bits should be set before Bit 15 (UAEN bit) is set to high.
SSA
12
3
Conversion between µ-law and A-law Enable
When this bit is low, normal switch without µ-law/A-law conversion. Connec-
tion memory high will be ignored.
When this bit is high, switch with µ-law/A-law conversion, and connection
memory high controls the conversion method.
Variable/Constant Delay Control
When this bit is low, the output data for this channel will be taken from con-
stant delay memory.
When this bit is set to high, the output data for this channel will be taken from
variable delay memory. Note that VAREN must be set in Control Register
first.
Source Stream Address
The binary value of these 5 bits represents the input stream number.
Source Channel Address
The binary value of these 8 bits represents the input channel number.
Connection Memory Mode = 0
If this is low, the connection memory is in the normal switching mode. Bit13 -
1 are the source stream number and channel number.
SSA
11
2
SSA
10
1
Zarlink Semiconductor Inc.
SSA
9
0
ZL50018
SCA
8
7
101
SCA
7
6
Description
SCA
6
5
SCA
5
4
SCA
4
3
SCA
3
2
SCA
2
1
SCA
1
0
Data Sheet
CMM
=0
0