ZL50018 ZARLINK [Zarlink Semiconductor Inc], ZL50018 Datasheet - Page 47

• Manufacturer Part Number: ZL50018
• Description: 2 K Digital Switch with Enhanced Stratum 3 DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

detected input reference frequency are used. In order to use programmed values for the monitor registers, MRLE
(bit 2) has to be set, in the eventuality that values other than Stratum 3 compliant values are desired.
16.0
The device provides access to the internal registers, connection memories and data memories via the
microprocessor port. The microprocessor port is capable of supporting both Motorola and Intel non-multiplexed
microprocessors. The microprocessor port consists of a 16-bit parallel data bus (D15 - 0), 14 bit address bus (A13 -
0) and six control signals (MOT_INTEL, CS, DS_RD, R/W_WR, IRQ and DTA_RDY).
The data memory can only be read from the microprocessor port. For a data memory read operation, D7 - 0 will be
used and D15 - 8 will output zeros.
For a CM_L read or write operation, all bits (D15 - 0) of the data bus will be used. For a CM_H write operation, D4 -
0 of the data bus must be configured and D15 - 5 are ignored. D15 - 5 must be driven either high or low. For a
CM_H read operation, D4 - 0 will be used and D15 - 5 will output zeros.
Refer to Figure 26 on page 108, Figure 27 on page 109, Figure 28 on page 110 and Figure 29 on page 111 for the
microprocessor timing.
17.0
The RESET pin is used to reset the ZL50018. When this pin is low, the following functions are performed:
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17.1
The recommended power-up sequence is for the V
power-up of the V
as V
synchronously puts the microprocessor port in a reset state
tristates the STio0 - 31 outputs
drives the STOHZ0 - 15 outputs to high
preloads all internal registers with their default values (refer to the individual registers for default values)
clears all internal counters
DD_IO
Power-up Sequence
Microprocessor Port
Device Reset and Initialization
, but should not “lead” the V
DD_CORE
supply (normally +1.8 V). The V
Far Upper Limit
Near Upper Limit
Nominal Value
Near Lower Limit
Far Lower Limit
Table 13 - Default Multi-period Hysteresis Limits
DD_IO
supply by more than 0.3 V.
Zarlink Semiconductor Inc.
ZL50018
DD_IO
Stratum 3 Default Values
47
supply (normally +3.3 V) to be established before the
DD_CORE
(in 10 ns units)
’h3B9A9DE8
’h3B9AC9FF
’h3B9AF0B8
-11.287 ppm
’h3B9AA346
‘h3B9AF616
11.287 ppm
-9.913 ppm
9.913 ppm
0 ppm
supply may be powered up at the same time
Data Sheet