ZL50018 ZARLINK [Zarlink Semiconductor Inc], ZL50018 Datasheet - Page 17

• Manufacturer Part Number: ZL50018
• Description: 2 K Digital Switch with Enhanced Stratum 3 DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

PBGA Pin
Number
B10
B11
LQFP Pin
Number
155
154
Pin Name
CKi
FPi
Zarlink Semiconductor Inc.
ST-BUS/GCI-Bus
Schmitt-Triggered Input)
This pin accepts the frame pulse which stays active for 61 ns,
122 ns or 244 ns at the frame boundary. The frame pulse
frequency is 8 kHz.
The frame pulse associated with the highest input or output data
rate must be applied to this pin when the device is operating in
Divided Slave mode or Master mode. The exception is if the device
is operating in Master mode with loopback (i.e., CKi_LP is set in
the Control Register). In that case, this input must be tied high or
low externally.
When the device is operating in Multiplied Slave mode, the frame
pulse associated with the highest input data rate must be applied
to this pin.
For all modes (except Master mode with loopback), if the data rate
is 16.384 Mbps, a 61 ns wide frame pulse must be used.
By default, the device accepts a negative frame pulse in ST-BUS
format, but it can accept a positive frame pulse instead if the
FPINP bit is set high in the Control Register (CR). It can accept a
GCI-formatted frame pulse by programming the FPINPOS bit in
the Control Register (CR) to high.
ST-BUS/GCI-Bus Clock Input (5 V-Tolerant Schmitt Triggered
Input)
This pin accepts a 4.096, 8.192 or 16.384 MHz clock.
The clock frequency associated with twice the highest input or
output data rate must be applied to this pin when the device is
operating in either Divided Slave mode or Master mode. The
exception is if the device is operating in Master mode with
loopback (i.e., CKi_LP is set in the Control Register). In that case,
this input must be tied high or low externally. The clock frequency
associated with twice the highest input data rate must be applied
to this pin when the device is operating in Multiplied Slave mode.
In all modes of operation (except Master mode with loopback),
when data is running at 16.384 Mbps, a 16.384 MHz clock must be
used. By default, the clock falling edge defines the input frame
boundary, but the device allows the clock rising edge to define the
frame boundary by programming the CKINP bit in the Control
Register (CR).
ZL50018
17
Frame
Description
Pulse
Input
(5 V-Tolerant
Data Sheet