ZL50018 ZARLINK [Zarlink Semiconductor Inc], ZL50018 Datasheet - Page 50

• Manufacturer Part Number: ZL50018
• Description: 2 K Digital Switch with Enhanced Stratum 3 DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

20.0
By programming the Stream Input Quadrant Frame Registers (SIQFR0 - 31), users can divide one frame of input
data into four quadrant frames and can force the LSB or MSB of every input channel in these quadrants to one or
zero for robbed-bit signaling. The four quadrant frames are defined as follows:
When the quadrant frame control bits, STIN[n]Q3C2 - 0 (bit 11 - 9), STIN[n]Q2C2 - 0 (bit 8 - 6), STIN[n]Q1C2 - 0 (bit
5 - 3) or STIN[n]Q1C2 - 0 (bit 2 - 0), are set, the LSB or MSB of every input channel in the quadrant is forced to “1”
or “0” as shown by the following table:
Note that Quadrant Frame Programming and BER reception cannot be used simultaneously on the same input
stream.
21.0
The JTAG test port is implemented to meet the mandatory requirements of the IEEE-1149.1 (JTAG) standard. The
operation of the boundary-scan circuitry is controlled by an external Test Access Port (TAP) Controller.
21.1
The Test Access Port (TAP) accesses the ZL50018 test functions. It consists of three input pins and one output pin
as follows:
•
•
Test Clock Input (TCK) - TCK provides the clock for the test logic. TCK does not interfere with any on-chip
clock and thus remains independent in the functional mode. TCK permits shifting of test data into or out of
the Boundary-Scan register cells concurrently with the operation of the device and without interfering with
the on-chip logic.
Test Mode Selection Inputs (TMS) - The TAP Controller uses the logic signals received at the TMS input to
control test operations. The TMS signals are sampled at the rising edge of the TCK pulse. This pin is
internally pulled to high when it is not driven from an external source.
Test Access Port (TAP)
16.384 Mbps
Quadrant Frame Programming
2.048 Mbps
4.096 Mbps
8.192 Mbps
JTAG Port
Data Rate
Note: y = 0, 1, 2, 3
STIN[n]Q[y]C[2:0]
100
101
0xx
110
111
Channel 0 - 15
Channel 0 - 31
Channel 0 - 63
Channel 0 - 7
Table 15 - Definition of the Four Quadrant Frames
Quadrant 0
Table 16 - Quadrant Frame Bit Replacement
Normal Operation
Replaces LSB of every channel in Quadrant y with ‘0’
Replaces LSB of every channel in Quadrant y with ‘1’
Replaces MSB of every channel in Quadrant y with ‘0’
Replaces MSB of every channel in Quadrant y with ‘1’
Zarlink Semiconductor Inc.
Channel 64 - 127
Channel 16 - 31
Channel 32 - 63
Channel 8 - 15
ZL50018
Quadrant 1
50
Action
Channel 128 - 191
Channel 32 - 47
Channel 64 - 95
Channel 16 - 23
Quadrant 2
Channel 192 - 255
Channel 96 - 127
Channel 48 - 63
Channel 24 - 31
Quadrant 3
Data Sheet