TSI-2 AGERE [Agere Systems], TSI-2 Datasheet - Page 58

• Manufacturer Part Number: TSI-2
• Description: 2k x 2k Time-Slot Interchanger
• Manufacturer: AGERE [Agere Systems]

TSI-2
2k x 2k Time-Slot Interchanger
8 Connection Store
The connection store RAM contains the per-time-slot control information for outgoing time slots. Each location in the RAM
corresponds to one outgoing time slot and contains all the time-slot specific control information for that time slot. The specific
address offset into the RAM is calculated as follows:
Address bits [14:7] are dependent on the destination (outgoing) CHI rate and should be calculated as follows, where TS is
the outgoing CHI time-slot number:
Table 8-1. Low_Control_Word (Read/Write)
The low-control word in the connection store has two functions. Normally, it is used to program the address of the incoming
time slot to which the outgoing time slot is connected. The outgoing time slot is implied by the connection store address as
described above. This normal switch operation will apply if the time-slot mode bits in the high-control word are set to low
latency or frame integrity switching modes. If alternate data mode is selected, the low control word contains the alternate
data (see
* Bits [15:0] have dual meaning based on the value in the Time_Slot_Mode field of the High_Control_Word (see Table 8-2).
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If the Time_Slot_Mode field is set to 10 (alternate data), then bits [15:0] have the following meaning:
Bits [7:0] are set to Alternate_Data_Pattern_1.
Bits [15:8] are set to Alternate_Data_Pattern_2.
If the Time_Slot_Mode field is set to anything other than 10, then bits [15:0] have the following meaning:
Bits [4:0] are set to Stream_Pointer.
Bits [12:5] are set to Time_Slot_Pointer.
Bits [15:13] are reserved.
0x10000—
ADDR[15] = 0.
ADDR[14:7] destination (outgoing) time-slot number of stream identified by address bits [6:2].
ADDR[6:2] destination (outgoing) stream (CHI) number.
ADDR[01] 0 = Low_Control, 1 = High_Control.
ADDR[00] = 0 (no byte addressability).
0x17FFC
Address
Table
16 MHz
8 MHz
4 MHz
2 MHz
Rate
15:8 Alternate_Data_Pattern_2. If alternate data is selected by the mode bits in the corre-
12:5 Time_Slot_Pointer. This field selects the desired time slot from the source stream (CHI).
8-2, bit [9:8]).
Bit
7:0
4:0
*
sponding high control location, the data in this byte will alternate with the
Alternate_Data_Pattern_1 pattern and be sent out on the transmit time slot.
This value is dependent on the speed (data rate) of the receive CHI specified by
Stream_Pointer and should be programmed as follows, where TS is the desired time-slot
number:
Alternate_Data_Pattern_1. If alternate data is selected by the mode bits in the corre-
sponding high control location, the data in this byte will alternate with the
Alternate_Data_Pattern_2 pattern and be sent out on the transmit time slot.
Stream_Pointer. This field selects one of 32 incoming streams.
TS x 2 (TS = 0—127)
TS x 4 (TS = 0—63)
TS x 8 (TS = 0—31)
Receive CHI Rate
TS (0—255)
16 Mbits/s
A[14:7]
8 Mbits/s
4 Mbits/s
2 Mbits/s
Name/Description
Time_Slot_Pointer [7:0]
TS x 2 (TS = 0—127)
TS x 4 (TS = 0—63)
TS x 8 (TS = 0—31)
TS (0—255)
Data Sheet, Revision 3
September 21, 2005
Agere Systems Inc.
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