TSI-2 AGERE [Agere Systems], TSI-2 Datasheet - Page 29

• Manufacturer Part Number: TSI-2
• Description: 2k x 2k Time-Slot Interchanger
• Manufacturer: AGERE [Agere Systems]

Data Sheet, Revision 3
September 21, 2005
Table 5-7. Microprocessor Port Timing—Write Cycle
Note: Posted writes follow the same timing shown in
Agere Systems Inc.
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
DATA[15:0]
ADDR[15:0]
return a DT prior to the device completing the write cycle. This allows the microprocessor to continue operation while
the device completes the write.
37
38
39
40
41
42
43
44
45
46
47
48
49
PAR[1:0]
MPUCLK
R/W
DT
CS
AS
Address Setup
Address Hold
Chip Select Setup
Chip Select Hold
Address Strobe Setup
Address Strobe Hold
R/W Setup
R/W Hold
Data Setup
Data Hold
DT High Impedance to Valid
DT Clock to Out
DT Valid to High Impedance
Figure 5-17. Microprocessor Port Timing—Write Cycle
t
t
t
t
t
47
37
39
41
43
t
t
38
42
Description
Figure 5-17 on page 29
t
45
and
t
48
Table 5-7 on page
2k x 2k Time-Slot Interchanger
Min
5
1
5
1
5
1
5
1
5
1
1
1
1
t
t
t
t
44
46
48
40
29. A posted write may
Max
15
—
—
—
—
—
—
—
—
—
—
7
8
t
49
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TSI-2
29