TSI-2 AGERE [Agere Systems], TSI-2 Datasheet - Page 56

• Manufacturer Part Number: TSI-2
• Description: 2k x 2k Time-Slot Interchanger
• Manufacturer: AGERE [Agere Systems]

TSI-2
2k x 2k Time-Slot Interchanger
Table 7-5. Connection_Store_Parity_Error_Address_Trap (CORWN)
As the connection store is continually read, its parity is checked. If an error is detected, the location with the error is saved
in this register and the Connection_Store_Parity_Error (see
mode, when this register is read, the Connection_Store_Parity_Error bit is cleared. If in clear-on-write (COW) mode, any
write to this register clears Connection_Store_Parity_Error.
Table 7-6. Receive_Link_Offset (Read Only)
This register displays the offset of the receive link with respect to the switch fabric. See also Transmit_Link_Offset and
Force_Transmit_Link_Offset in Table 7-7.
Table 7-7. Transmit_Link_Offset (Read/Write)
This register displays/controls the offset of the transmit links with respect to the switch fabric. Normally, the
Transmit_Link_Offset is determined by the CHI frame synchronization's relative position to the switch fabric synchronization.
In this case, bit [15] of this register should be set to 0.
56
56
Address
Address
Address
0x0114C
0x01146
0x01148
15:12 Unused.
14:12 Unused.
14:0 Connection_Store_Parity_Error_Address. This bit field contains the address within the
11:0 Link_Offset. This field contains the time-slot offset of the receive link.
11:0 Transmit_Offset. If Force_Transmit_Link_Offset is set to 1, this value will force the switch
Bit
Bit
Bit
15
15
Unused.
connection store with a parity error. The address of the first error (after a clear) is sampled
and saved.
Force_Transmit_Link_Offset.
0 = Allows the switch fabric to self-determine its offsets.
1 = Forces the device to use the Transmit_Offset value to align the switch fabric to a deter-
fabric to align itself this many time slots off from the CHI frame synchronization. Please con-
tact your FAE if you plan on using this feature.
ministic position relative to the CHI frame synchronization. If this is set to 1, this register
value should be set and the system allowed to stabilize (more than 250 µs) prior to read-
ing the value in Receive_Link_Offset (see Table 7-6).
Name/Description
Name/Description
Name/Description
Table 7-1 on page
54) error bit is set. If in clear-on-read (COR)
Data Sheet, Revision 3
September 21, 2005
Agere Systems Inc.
Default
Default
Default
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