TSI-2 AGERE [Agere Systems], TSI-2 Datasheet - Page 21

• Manufacturer Part Number: TSI-2
• Description: 2k x 2k Time-Slot Interchanger
• Manufacturer: AGERE [Agere Systems]

Data Sheet, Revision 3
September 21, 2005
Note: This figure assumes the device is programmed to sample FSYNC on the rising edge of CHICLK.
Table 5-4. CHI Interface Timing
* Applies if Driver_Enable_Control = 01. For Driver_Enable_Control = 11 refer to
All timing specifications apply under the following conditions:
Agere Systems Inc.
Parameter
If FS is active-low.
If the falling edge of CHICLK is specified as the active edge.
At all RXD and TXD rates (16.384 Mbits/s, 8.192 Mbits/s, 4.096 Mbits/s, or 2.048 Mbits/s) with a CHICLK frequency of
16.384 MHz or 8.192 MHz.
t
t
t
t
t
t
t
13
14
15
16
17
18
19
CHICLK
FSYNC
RXD
TXD
FSYNC Setup Time to Active CHICLK Edge
FSYNC Hold Time from Active CHICLK Edge
RXD Setup to Active CHICLK Edge
RXD Hold Time from Active CHICLK Edge
TXD High Z to Data Valid
TXD Propagation Delay from Active CHICLK Edge
Transmit Data High Impedance*
t
t
13
15
t
17
t
t
14
16
t
18
Description
Figure 5-4. CHI Interface Timing
t
19
Figure 5-15, CHI 3-State Output Control on page
2k x 2k Time-Slot Interchanger
Min
10
10
—
—
5
5
2
Max
15
12
15
—
—
—
—
27.
Unit
ns
ns
ns
ns
ns
ns
ns
TSI-2
21