TSI-2 AGERE [Agere Systems], TSI-2 Datasheet - Page 23

• Manufacturer Part Number: TSI-2
• Description: 2k x 2k Time-Slot Interchanger
• Manufacturer: AGERE [Agere Systems]

Data Sheet, Revision 3
September 21, 2005
Note: For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the CHICLK.
Note: For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the CHICLK.
Agere Systems Inc.
FSYNC
CHICLK
FSYNC
CHICLK
w/ TS offset = 127,
w/ TS offset = 127,
w/ TS offset = 13,
w/ TS offset = 1,
w/ TS offset = 1,
w/ bit offset = 1
w/ bit offset = 1
w/ 2¾ bit offset
w/ bit offset = 7
bit offset = 7¾
bit offset = 3¼
bit offset = 7¾
w/ ¼ bit offset
w/ ½ bit offset
w/ ¼ bit offset
w/ ½ bit offset
w/ ¾ bit offset
bit offset = 0
bit offset = 0
w/ 0 offset
w/ 0 offset
Figure 5-7. Typical Receive CHI Timing with 8.192 Mbits/s Data and 16.384 MHz CHICLK
Figure 5-8. Transmit CHI Timing with 8.192 Mbits/s Data and 16.384 MHz CHICLK
TS 127 B6
TS 127 B5
TS 126 B6
TS 127 B6
TS 127 B4
TS 127 B7
TS127 B6
TS127 B7
TS127 B6
TS127 B0
TS126 B7
TS127 B6
TS127 B7
TS114 B4
TS127 B7
TS127 B7
TS127 B7
TS127 B6
TS126 B7
TS127 B7
TS127 B5
TS0 B0
TS127 B7
TS127 B7
TS127 B1
TS127 B0
TS0 B0
TS127 B7
TS114 B5
TS0 B0
data sampled
data sampled
data sampled
data sampled
TS0 B0
TS0 B0
data sampled
data sampled
TS127 B7
TS127 B0
TS127 B6
TS0 B0
TS0 B0
TS0 B1
data sampled
TS127 B2
TS127 B1
TS0 B0
TS0 B1
TS0 B0
data sampled
data sampled
data sampled
TS114 B6
TS0 B0
TS0 B1
TS0 B1
TS0 B1
TS127 B1
TS127 B7
TS0 B1
TS0 B0
TS0 B1
TS0 B2
TS127 B3
TS127 B2
TS0 B1
TS0 B2
TS0 B1
TS114 B7
TS0 B1
TS0 B2
TS0 B2
TS0 B2
2k x 2k Time-Slot Interchanger
TS127 B2
TS0 B2
TS0 B1
TS0 B2
TS0 B0
TS0 B3
TS127 B4
TS127 B3
TS0 B2
TS0 B3
TS0 B2
TS115 B0
TS0 B2
TS0 B3
TS0 B3
TS0 B3
TS127 B3
TS0 B3
TS0 B2
TS0 B3
TS0 B1
TS0 B4
TS127 B5
TS127 B4
TS0 B3
TS0 B4
TS0 B3
TS115 B1
TS0 B3
TS0 B4
TSI-2
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