TSI-2 AGERE [Agere Systems], TSI-2 Datasheet - Page 50

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TSI-2

Manufacturer Part Number
TSI-2
Description
2k x 2k Time-Slot Interchanger
Manufacturer
AGERE [Agere Systems]
Datasheet
TSI-2
2k x 2k Time-Slot Interchanger
Table 6-48. Transmit_CHI_Configuration (Read/Write)
Each of the incoming CHIs can be independently designed and programmed with a unique offset from the master frame
synchronization. This bank of registers works in conjunction with the corresponding Transmit_CHI_Time_Slot_Offset regis-
ters (see
50
50
0x00C00—0x00C3E
Address
Table 6-53 on page
13:12 Driver_Enable_Control. These two bits determine how the output TXD pin is
11:10 Unused.
Bit
9:8 Transmit_CHI_Bit_Rate. These bits indicate the data rate of this transmit CHI.
6:4 Transmit_CHI_Bit_Offset. These bits represent the bit offset relative to the frame
3:2 Unused.
15
14
7
1
0
RECEIVE_CHI_LOOPBACK_ENABLE
CHI_Feedback_Source_Selection. Selects which data is sent to corresponding
receive CHI.
0 = Means pre-output data is sent.
1 = Means the input from the bidirectional TXD pin is sent. This bit has no effect
Unused.
actually driven.
00 = Always disabled.
01 = Based on time-slot programming (timing from CHICLK).
10 = Reserved.
11 = Similar to 01 except all time slots are disabled near end of time slot (see
00 = 2 Mbits/s.
01 = 4 Mbits/s.
10 = 8 Mbits/s.
11 = 16 Mbits/s (only valid with 16 MHz CHICLK).
Unused.
synchronization sample point for this transmit CHI (in binary, 0—7 bits).
Transmit_CHI_Half_Bit_Offset.
0 = No additional delay.
1 = Indicates an additional 1/2 bit of offset for this transmit CHI.
Transmit_CHI_Quarter_Bit_Offset.
0 = No additional delay.
1 = Indicates an additional 1/4 bit of offset for this transmit CHI. This bit must be 0
RXD
53) to provide this control. These registers provide the bit and fractional bit offset control.
unless the corresponding receive CHI's Receive_CHI_Loopback_Enable bit is
one (see
when the CHI rate is 16 Mbits/s or when the CHI rate is 8 Mbits/s mode and the
CHICLK is 8.192 MHz.
Transmit_High_Impedance_Delay in
Figure 6-1. Transmit CHI Configuration (R/W)
Table 6-44 on page
CHI_FEEDBACK_SOURCE_SELECTION
SWITCH FABRIC
Name/Description
48).
Table 6-51 on page 52
TXD
Data Sheet, Revision 3
bits [6:4]).
September 21, 2005
Agere Systems Inc.
Default
000
00
00
0
0
0

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