TSI-2 AGERE [Agere Systems], TSI-2 Datasheet - Page 37

• Manufacturer Part Number: TSI-2
• Description: 2k x 2k Time-Slot Interchanger
• Manufacturer: AGERE [Agere Systems]

Data Sheet, Revision 3
September 21, 2005
Table 6-15. Global_Control (Read/Write)
Agere Systems Inc.
Address Bit
0x0000C 15 Software_Reset. This bit forces and holds the device in reset.
14:9 Unused.
7:5 Unused.
8
4
3
2
1
0
0 = Normal.
1 = Reset.
Reserved.
DT_Wait_State_Control. During write posting, a data transfer acknowledge (DT) can be
generated on the first or second cycle following address strobe. If a DT immediately following
address strobe is too fast for the microprocessor, then a single wait-state can be inserted.
0 = Zero wait-states inserted.
1 = One wait-state inserted.
Write_Posting_Enable. This bit enables write posting, which will provide an early DT to the
microprocessor.
0 = Write posting disabled.
1 = Write posting enabled.
Saturate_Rollover_Select. This control bit changes the behavior of event counter registers. In
saturation mode, a register will stick at the maximum value once it is reached. In roll-over mode,
an event register will continue counting as its value cycles back to zero.
0 = Roll over.
1 = Saturation.
When in saturate mode, the counters will operate in a clear-on-read mode. When in the roll-over
mode, the counters will not be directly writable.
Data_Parity_Mode. This bit controls the parity setting and checking on the microprocessor data
bus.
Register_Clearing_Mode. This bit controls the way clearing is performed on status bits in clear-
on-read/clear-on-write registers.
0 = The status bit is cleared by writing a 1 to it.
1 = The status bit is cleared when a microprocessor read is performed.
0 = Even parity on microprocessor byte data/parity bus.
1 = Odd parity on microprocessor byte data/parity bus.
Name/Description
2k x 2k Time-Slot Interchanger
Default
TSI-2
—
—
—
0
1
0
0
0
0
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