TSI-2 AGERE [Agere Systems], TSI-2 Datasheet - Page 41

• Manufacturer Part Number: TSI-2
• Description: 2k x 2k Time-Slot Interchanger
• Manufacturer: AGERE [Agere Systems]

Data Sheet, Revision 3
September 21, 2005
Table 6-27. CSG_Seed_Low (Read/Write)
Seed value for the pseudorandom pattern generator for the low word of the connection store RAM.
Table 6-28. CSG_Seed_High (Read/Write)
Seed value for the pseudorandom pattern generator for the high word of the connection store RAM.
Table 6-29. CSG_OR_Mask_Low (Read/Write)
This register allows bits in the connection store to be forced to 1. CS[15:0] = (pseudorandom data [15:0] OR
CSG_OR_Mask_Low) AND CSG_AND_Mask_Low, bit enabled by CSG_Write_Enable_Low.
Table 6-30. CSG_OR_Mask_High (Read/Write)
This register allows bits in the connection store to be forced to 1. CS[31:16] = (pseudorandom data [31:16] OR
CSG_OR_Mask_High) AND CSG_AND_Mask_High, bit enabled by CSG_Write_Enable_High.
Note: CS[22:18] are always 0.
Agere Systems Inc.
Address
Address
Address
Address
0x00410
0x00412
0x00418
0x0041A
15:0 CSG_Seed_Low. If the LFSR_Seed_Control bit (see
15:0 CSG_OR_Mask_Low. This register allows bit fields in the connection store to be forced to a
15:7 CSG_OR_Mask_High_B. This register allows bit fields in the connection store to be forced
14:0 CSG_Seed_High. If the LFSR_Seed_Control bit (see
6:2
1:0
Bit
Bit
Bit
Bit
15
the beginning of a CSG operation, bits [15:0] of the LFSR supplying the connection store
RAM with data are loaded with this programmable seed.
Unused.
ning of a CSG operation, bits [30:16] of the LFSR supplying the connection store RAM with
data are loaded with this programmable seed.
one during a CSG fill operation. A bit-wise OR of this register and bits [15:0] of the pseudo-
random generated data are performed to obtain the data for connection store. The resultant
is then ANDed with CSG_AND_Mask_Low.
to a 1 during a CSG fill operation. A bit-wise OR of this register and bits [31:23] of the pseu-
dorandom generated data are performed to obtain the data for connection store. The result-
ant is then ANDed with CSG_AND_Mask_High.
Unused.
CSG_OR_Mask_High_A. This register allows bit fields in the connection store to be forced
to a 1 during a CSG fill operation. A bit-wise OR of this register and bits [17:16] of the pseu-
dorandom generated data are performed to obtain the data for connection store. The result-
ant is then ANDed with CSG_AND_Mask_High.
Name/Description
Name/Description
Name/Description
Name/Description
Table 6-21 on page
Table
6-21) is asserted, at the begin-
2k x 2k Time-Slot Interchanger
39) is asserted, at
0xFFFF
Default
Default
0x7FFF
Default
Default
0x0000
0x000
TSI-2
00
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