TSI-2 AGERE [Agere Systems], TSI-2 Datasheet - Page 26

• Manufacturer Part Number: TSI-2
• Description: 2k x 2k Time-Slot Interchanger
• Manufacturer: AGERE [Agere Systems]

TSI-2
2k x 2k Time-Slot Interchanger
Note: For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the CHICLK.
Notes:
1/4 bit offset not valid with 8 MHz data and 8 MHz clock.
For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the
CHICLK.
26
26
FSYNC
CHICLK
FSYNC
CHICLK
w/ TS offset = 127,
w/ TS offset = 127,
w/ TS offset = 13,
w/ TS offset = 1,
w/ bit offset = 1
w/ bit offset = 7
w/ TS offset = 1,
w/ 2¾ bit offset
w/ bit offset = 1
w/ ¼ bit offset
w/ ½ bit offset
w/ ¾ bit offset
bit offset = 3¼
bit offset = 7¾
bit offset = 7½
w/ ½ bit offset
bit offset = 0
bit offset = 0
w/ 0 offset
w/ 0 offset
Figure 5-13. Typical Receive CHI Timing with 8.192 Mbits/s Data and 8.192 MHz CHICLK
Figure 5-14. Transmit CHI Timing with 8.192 Mbits/s Data and 8.192 MHz CHICLK
TS127 B5
TS127 B3
TS127 B6
TS127 B5
TS127 B4
TS126 B5
TS127 B6
TS127 B5
TS126 B7
TS126 B6
TS127 B6
TS114 B3
TS127 B5
TS127 B6
TS127 B6
TS127 B6
TS127 B5
TS126 B6
TS127 B6
TS127 B4
TS127 B7
TS127 B7
TS127 B6
TS127 B0
TS126 B7
TS127 B6
TS127 B7
TS127 B7
TS114 B4
TS127 B7
TS127 B7
TS127 B6
TS126 B7
TS127 B7
TS127 B5
TS0 B0
TS127 B7
TS127 B1
TS127 B0
TS0 B0
TS127 B7
TS114 B5
TS0 B0
TS0 B0
data sampled
data sampled
data sampled
data sampled
TS0 B0
TS127 B7
TS127 B0
TS127 B6
TS0 B0
data sampled
data sampled
TS0 B0
TS0 B1
TS127 B2
TS127 B1
data sampled
TS0 B1
TS0 B0
TS0 B0
TS0 B1
TS114 B6
data sampled
data sampled
data sampled
TS0 B1
TS0 B1
TS127 B1
TS0 B1
TS0 B0
TS127 B7
TS0 B1
TS0 B2
TS127 B3
TS127 B2
TS0 B2
TS0 B1
TS0 B1
TS0 B2
TS114 B7
TS0 B2
TS127 B2
TS0 B2
TS0 B2
TS0 B1
TS0 B2
TS0 B0
TS0 B3
TS127 B4
TS127 B3
TS0 B3
TS0 B2
TS0 B2
TS0 B3
TS115 B0
TS0 B3
TS127 B3
TS0 B3
TS0 B3
TS0 B2
TS0 B3
TS0 B1
TS0 B4
TS127 B5
TS127 B4
TS0 B4
TS0 B3
TS0 B3
TS0 B4
TS115 B1
TS0 B4
TS127 B4
TS0 B4
TS0 B4
TS0 B3
TS0 B4
TS0 B2
TS0 B5
TS127 B6
TS127 B5
TS0 B4
TS0 B4
TS0 B5
TS0 B5
TS115 B2
TS0 B5
TS127 B5
TS0 B5
TS0 B4
TS0 B5
TS0 B5
TS0 B3
TS0 B6
TS127 B7
TS127 B6
Data Sheet, Revision 3
TS115 B3
September 21, 2005
TS0 B7
TS127 B7
TS0 B 0
TS115 B4
Agere Systems Inc.
TS1 B0
TS0 B1
TS0 B0
TS115 B5