TSI-2 AGERE [Agere Systems], TSI-2 Datasheet - Page 43

• Manufacturer Part Number: TSI-2
• Description: 2k x 2k Time-Slot Interchanger
• Manufacturer: AGERE [Agere Systems]

Data Sheet, Revision 3
September 21, 2005
Table 6-34. CSG_Configuration (Read/Write)
This register is used to populate the specified connection store RAM fields when the CSG is in the N-to-N mapping mode.
This register is not used when in the LFSR pattern mode (see CSG_Mode_Select on
Agere Systems Inc.
Address
0x0042A
15:11 Reserved.
9:8
6:0
Bit
10
7
TPM_Enable_Field_Fill. The Test_Pattern_Monitor_Enable field (see
page
Mode_Field_Fill. The Time_Slot_Mode bits (see
with this pattern.
00 = Low latency.
01 = Frame integrity.
10 = Alternate data.
11 = TGP data.
High_Impedance_Control_Field_Fill. Fills the Time_Slot_High_Impedance control bit
(see
Unused.
Table
59) in the connection store RAM is filled with this value.
8-2) in the connection store.
Name/Description
Table
8-2) in the connection store are filled
2k x 2k Time-Slot Interchanger
Table 6-21 on page 39
Table 8-2 on
bit 1).
Default
00000
TSI-2
00
—
0
0
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