TSI-2 AGERE [Agere Systems], TSI-2 Datasheet - Page 48

• Manufacturer Part Number: TSI-2
• Description: 2k x 2k Time-Slot Interchanger
• Manufacturer: AGERE [Agere Systems]

TSI-2
2k x 2k Time-Slot Interchanger
6.8 Concentration Highway Configuration Registers
Table 6-44. Receive_CHI_Configuration (Read/Write)
Each of the incoming CHIs can be independently designed and programmed with a unique offset from the master frame
synchronization. This bank of registers works in conjunction with the corresponding Receive_CHI_Time_Slot_Offset regis-
ters (see
Table 6-45. Receive_CHI_Status (CORWN) Receive_CHI_Status (CORWN)
48
48
0x00A00—0x00A3E
Address
0x00A80
Address
Table 6-52 on page
15:3 Unused.
Bit
2
1
0
Receive_Clock_Error.
0 = No clock error detected.
1 = Indicates a slow (or missing) CHICLK.
Receive_Lock_Error.
0 = No clock error detected.
1 = Indicates a synchronization error has occurred between the CHICLK and the internal
Receive_Frame_Sync_Error.
0 = No frame synchronization error detected.
1 = Indicates a frame synchronization error has occurred. This means the CHI frame
14:10 Unused.
PLL clock. If Enable_Receive_CHI_Automatic_Resynchronization (see
page
(Force_Receive_CHI_Resynchronization, see
synchronization was either missing or misplaced. For missing frame synchronizations,
this status is the only action taken. For misplaced frame synchronizations, the device
automatically synchronizes to the new frame synchronization position.
9:8
6:4
3:2
Bit
15
7
1
0
49) is not a 1, then a manual resynchronization should be performed
53) to provide this control. These registers provide the bit and fractional bit offset control.
Receive_CHI_Loopback_Enable.
0 = Input data for this receive CHI comes from the corresponding RXD pin.
1 = Input data for this receive CHI comes from the corresponding transmit CHI (see
Receive_CHI_Bit_Rate. These bits indicate the data rate of this receive CHI.
00 = 2 Mbits/s.
01 = 4 Mbits/s.
10 = 8 Mbits/s.
11 = 16 Mbits/s. (Only valid with 16 MHz CHICLK clock.)
Unused.
Receive_CHI_Bit_Offset. These bits represent the bit offset relative to the frame
synchronization sample point for this receive CHI (in binary, 0—7 bits).
Unused.
Receive_CHI_Half_Bit_Offset.
0 = No additional offset.
1 = Indicates an additional 1/2 bit of offset for this receive CHI.
Receive_CHI_Quarter_Bit_Offset.
0 = No additional offset.
1 = Indicates an additional 1/4 bit of offset for this receive CHI.
CHI_Feedback_Source_Selection in
Name/Description
Name/Description
Table
Table 6-48 on page 50
6-47).
Data Sheet, Revision 3
bit 15).
Table 6-47 on
September 21, 2005
Agere Systems Inc.
Default
Default
—
—
—
—
000
00
—
—
—
0
0
0