TSI-2 AGERE [Agere Systems], TSI-2 Datasheet - Page 40

• Manufacturer Part Number: TSI-2
• Description: 2k x 2k Time-Slot Interchanger
• Manufacturer: AGERE [Agere Systems]

TSI-2
2k x 2k Time-Slot Interchanger
Table 6-22. CSG_Status (Read Only)
This register provides general status of the connection store generator.
Table 6-23. CSG_Starting_Address (Read/Write)
This register defines the starting address of the connection store RAM for the CSG.
Table 6-24. CSG_Ending_Address (Read/Write)
This register defines the ending address of the connection store RAM for the CSG.
Table 6-25. CSG_Write_Enable_Low (Read/Write)
This register provides write enable control on a per-bit basis for the low word of the connection store when using the CSG
to fill the connection store RAM.
Table 6-26. CSG_Write_Enable_High (Read/Write)
This register provides write enable control on a per-bit basis for the high word of the connection store when using the CSG
to fill the connection store RAM.
40
40
Address Bit
0x0040A 15:0 CSG_Bit_Write_Enable_High. Controls writing of bits [31:16] in the connection store memory.
Address
Address
Address
Address
0x00402
0x00404
0x00406
0x00408
15:13 Unused.
15:13 Unused.
15:0 CSG_Bit_Write_Enable_Low. Controls writing of bits [15:0] in the connection store memory.
15:1 Unused.
12:0 CSG_Start_Address. Connection store updates will start at this address. To apply the start
12:0 CSG_End_Address. Connection store updates will end at this address. To apply the end
Bit
Bit
Bit
Bit
0
0 = Ignore the corresponding bit (this bit in memory maintains its present value).
1 = Write the corresponding bit.
0 = Ignore the corresponding bit (this bit in memory maintains its present value).
1 = Write the corresponding bit.
CSG_Operation_Complete. Pattern generation for connection and data store is complete.
The bit is normally asserted, but it is deasserted when the CSG update is in progress. This
status bit is cleared when the CSG_Enable bit (see
0 = Pattern generator is busy.
1 = Pattern generation is finished.
address to a single CS memory, disable the bit write enable register bits for the other CS
memory.
address to a single CS memory, disable the bit write enable register bits for the other CS
memory.
Name/Description
Name/Description
Name/Description
Name/Description
Name/Description
Table
6-21) is cleared.
Data Sheet, Revision 3
September 21, 2005
Agere Systems Inc.
0xFFFF
Default
Default
Default
0x1FFF
Default
0x0000
0xFFFF
Default
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