TSI-2 AGERE [Agere Systems], TSI-2 Datasheet - Page 25

• Manufacturer Part Number: TSI-2
• Description: 2k x 2k Time-Slot Interchanger
• Manufacturer: AGERE [Agere Systems]

Data Sheet, Revision 3
September 21, 2005
Note: For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the CHICLK.
Note: For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the CHICLK.
Agere Systems Inc.
FSYNC
CHICLK
FSYNC
CHICLK
w/ TS offset = 31,
w/ TS offset = 13,
w/ TS offset = 31,
w/ TS offset = 1,
w/ TS offset = 1,
w/ bit offset = 1
w/ bit offset = 1
w/ 2¾ bit offset
w/ bit offset = 7
w/ ¼ bit offset
w/ ½ bit offset
bit offset = 7¾
bit offset = 3¼
bit offset = 7¾
w/ ¼ bit offset
w/ ½ bit offset
w/ ¾ bit offset
bit offset = 0
bit offset = 0
w/ 0 offset
w/ 0 offset
Figure 5-11. Typical Receive CHI Timing with 2.048 Mbits/s Data and 16.384 MHz CHICLK
Figure 5-12. Transmit CHI Timing with 2.048 Mbits/s Data and 16.384 MHz CHICLK
TS31 B7
TS31 B7
TS31 B7
TS31 B6
TS30 B7
TS31 B7
TS31 B5
TS0 B0
TS31 B7
TS31 B7
TS31 B1
TS31 B0
TS0 B0
TS31 B7
TS18 B5
data sampled
data sampled
data sampled
data sampled
TS0 B0
TS0 B0
TS0 B0
data sampled
data sampled
TS31 B7
TS31 B0
TS0 B0
TS31 B6
TS0 B0
TS0 B1
data sampled
2k x 2k Time-Slot Interchanger
TS0 B0
TS31 B2
TS31 B1
TS0 B1
TS0 B0
data sampled
data sampled
data sampled
TS0 B0
TS18 B6
TS0 B1
TS0 B1
TS0 B1
TS31 B01
TS0 B1
TS0 B0
TS31
TS0
TS0
TSI-2
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