TSI-2 AGERE [Agere Systems], TSI-2 Datasheet - Page 49

• Manufacturer Part Number: TSI-2
• Description: 2k x 2k Time-Slot Interchanger
• Manufacturer: AGERE [Agere Systems]

Data Sheet, Revision 3
September 21, 2005
Table 6-46. Receive_CHI_Status_Mask (Read/Write)
Mask bits for the Receive_CHI_Status register (see
Table 6-47. Receive_CHI_Global_Configuration (Read/Write)
Global configuration control for all the receive CHIs.
Agere Systems Inc.
Address
Address
0x00A82
0x00A84
15:3 Unused.
15:4 Unused.
Bit
Bit
2
1
0
3
2
1
0
Receive_Clock_Error_Mask.
0 = The Receive_Clock_Error bit (see
1 = The Receive_Clock_Error bit is blocked from causing an interrupt.
Receive_Lock_Error_Mask.
0 = The Receive_Lock_Error bit (see
1 = The Receive_Lock_Error bit is blocked from causing an interrupt.
Receive_Frame_Sync_Error_Mask.
0 = The Receive_Frame_Sync_Error bit (see
1 = The Receive_Frame_Sync_Error bit is blocked from causing an interrupt.
Force_Receive_CHI_Resynchronization.
0 = Normal operation.
1 = This forces the receive CHI/PLL interface to resynchronize.
Enable_Receive_CHI_Automatic_Resynchronization.
0 = The device will inhibit automatic resynchronization of the receive CHI/PLL interface if it
1 = The device will automatically resynchronize the receive CHI/PLL interface if it detects it
Receive_Frame_Sync_Polarity. This bit indicates the polarity of the frame synchronization
signal.
0 = Indicates the frame synchronization is active-low. The reference point for all receive CHI
1 = Indicates the frame synchronization is active-high.
Receive_Clock_Edge. This bit indicates which edge of the CHICLK to use to sample the
frame synchronization signal.
0 = Indicates sampling on the falling edge. This also defines the reference point for all
1 = Indicates sampling on the rising edge of the clock.
masked at a higher level).
masked at a higher level).
(unless masked at a higher level).
detects it is out-of-synchronization (not recommended).
is out-of-synchronization.
timing is the first active edge of CHICLK (see Receive_Clock_Edge) after the frame
synchronization transitions to the active level as defined here.
receive CHI timing and offsets.
Table
Name/Description
Name/Description
Table
6-45).
Table
6-45) will cause an interrupt if active (unless
6-45) will cause an interrupt if active (unless
Table
6-45) will cause an interrupt if active
2k x 2k Time-Slot Interchanger
Default
Default
TSI-2
—
—
1
1
1
0
0
0
0
49