TSI-2 AGERE [Agere Systems], TSI-2 Datasheet - Page 24

• Manufacturer Part Number: TSI-2
• Description: 2k x 2k Time-Slot Interchanger
• Manufacturer: AGERE [Agere Systems]

TSI-2
2k x 2k Time-Slot Interchanger
Note: For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the CHICLK.
Note: For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the CHICLK.
24
24
FSYNC
CHICLK
FSYNC
CHICLK
w/ TS offset = 13,
w/ TS offset = 63,
w/ TS offset = 63,
w/ TS offset = 1,
w/ TS offset = 1,
w/ bit offset = 1
w/ bit offset = 1
w/ 2¾ bit offset
w/ bit offset = 7
bit offset = 3¼
bit offset = 7¾
w/ ¼ bit offset
w/ ½ bit offset
bit offset = 7¾
w/ ¼ bit offset
w/ ½ bit offset
w/ ¾ bit offset
bit offset = 0
bit offset = 0
w/ 0 offset
w/ 0 offset
Figure 5-9. Typical Receive CHI Timing with 4.096 Mbits/s Data and 16.384 MHz CHICLK
Figure 5-10. Transmit CHI Timing with 4.096 Mbits/s Data and 16.384 MHz CHICLK
TS63 B7
TS50 B4
TS63 B6
TS63 B7
TS63 B7
TS63 B7
TS63 B5
TS63 B7
TS63 B6
TS62 B7
TS0 B0
TS63 B7
TS63 B1
TS63 B0
TS63 B7
TS0 B0
TS50 B5
TS63 B7
TS0 B0
data sampled
data sampled
data sampled
data sampled
TS0 B0
TS0 B0
data sampled
data sampled
TS63 B6
TS63 B7
TS63 B0
TS0 B0
TS0 B1
TS0 B0
data sampled
TS63 B2
TS63 B1
TS0 B1
TS0 B0
TS0 B0
data sampled
data sampled
data sampled
TS50 B6
TS0 B1
TS0 B0
TS0 B1
TS0 B1
TS63 B7
TS63 B1
TS0 B1
TS0 B2
TS0 B1
TS0 B0
Data Sheet, Revision 3
September 21, 2005
TS63 B3
TS63 B2
TS0 B2
TS0 B1
TS0 B1
Agere Systems Inc.
TS50 B7
TS0 B2
TS0 B1
TS0 B2
TS0 B2