TSI-2 AGERE [Agere Systems], TSI-2 Datasheet - Page 35

• Manufacturer Part Number: TSI-2
• Description: 2k x 2k Time-Slot Interchanger
• Manufacturer: AGERE [Agere Systems]

Data Sheet, Revision 3
September 21, 2005
Table 6-11. Summary_Interrupt_Status (Read Only)
Table 6-12. Summary_Interrupt_Mask (Read/Write)
Agere Systems Inc.
Address
Address
0x00004
0x00006
15:6 Unused.
15:6 Unused.
Bit
Bit
5
4
3
2
1
0
5
4
3
2
1
0
Transmit_CHI_Interrupt. Active-high flag indicating an unmasked error or status is present
in the Transmit_CHI_Status register (see
0 = No transmit CHI error(s) detected.
1 = Transmit CHI Error(s) detected.
Receive_CHI_Interrupt. Active-high flag indicating that an unmasked error or status is
present in the Receive_CHI_Status register (see
0 = No receive CHI error(s) detected.
1 = Receive CHI error(s) detected.
Unused.
TPM_Interrupt. Active-high flag indicating an unmasked error or status is present in the
TPM_Status register (see
0 = No test pattern monitor error(s) detected.
1 = Test pattern error(s) detected.
SF_Interrupt. Active-high flag indicating an unmasked error is present in the SF_Status reg-
ister (see
0 = No switch fabric error(s) detected.
1 = Switch fabric error(s) detected.
CPU_Access_Interrupt. Active-high flag indicating an unmasked error has been detected
by the CPU_Access_Error register (see
0 = No microprocessor access error(s) detected.
1 = Microprocessor access error(s) detected.
Transmit_CHI_Interrupt_Mask.
0 = The Transmit_CHI_Interrupt bit (see Table 6-11) will cause an interrupt if active.
1 = The Transmit_CHI_Interrupt bit is blocked from causing an interrupt.
Receive_CHI_Interrupt_Mask.
0 = The Receive_CHI_Interrupt bit (see Table 6-11) will cause an interrupt if active.
1 = The Receive_CHI_Interrupt bit is blocked from causing an interrupt.
Unused.
TPM_Interrupt_Mask.
0 = The TPM_Interrupt bit (see Table 6-11) will cause an interrupt if active.
1 = The TPM_Interrupt bit is blocked from causing an interrupt.
SF_Interrupt_Mask.
0 = The SF_Interrupt bit will (see Table 6-11) cause an interrupt if active.
1 = The SF_Interrupt bit is blocked from causing an interrupt.
CPU_Access_Interrupt_Mask.
0 = The CPU_Access_Interrupt bit (see Table 6-11) will cause an interrupt if active.
1 = The CPU_Access_Interrupt bit is blocked from causing an interrupt.
Table 7-1 on page
Table 6-42 on page
54).
Name/Description
Name/Description
Table 6-13 on page
Table 6-49 on page
47).
Table 6-45 on page
36).
51).
2k x 2k Time-Slot Interchanger
48).
Default
Default
TSI-2
—
—
—
—
—
—
—
—
—
1
1
1
1
1
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