TSI-2 AGERE [Agere Systems], TSI-2 Datasheet - Page 12

• Manufacturer Part Number: TSI-2
• Description: 2k x 2k Time-Slot Interchanger
• Manufacturer: AGERE [Agere Systems]

TSI-2
2k x 2k Time-Slot Interchanger
2.4 Ball Types
This table describes each type of input, output, and I/O ball used in the device.
Table 2-4. Ball Types
2.5 Ball Definitions
This section describes the function of each of the device balls. The balls are listed by ball name. The static parameters (drive
currents, switching thresholds, etc.) for each ball type (input, output, etc.) are described in
Table
Table 2-5. Timing Port
Table 2-6. Transmit and Receive Concentration Highways
12
12
Ball Name Type
Ball Name Type
RXD[31:0] I pd Receive Data [31:0]. Receive concentration highways. These are serial, synchronous data streams,
TXD[31:0]
CKSPD0
CKSPD1
CHICLK
FSYNC
Type Label
4-3.
O od
I pd
I pu
I/O
O
P
I
I pd Clock Speed. Reserved, leave disconnected. 20 kΩ pull-down resistor.
O
I
I
I
CMOS input, TTL switching thresholds.
CMOS input, TTL switching thresholds with internal pull-down resistor.
CMOS input, TTL switching thresholds with internal pull-up resistor.
CMOS output.
Open-drain output.
Bidirectional ball. CMOS input with TTL switching thresholds and CMOS output.
Power and ground.
which may be individually programmed to operate at 2.048 Mbits/s, 4.096 Mbits/s, 8.192 Mbits/s, or
16.384 Mbits/s. They carry 32, 64, 128, or 256 time slots (respectively) each occupying eight
contiguous bits. 20 kΩ pull-down resistor.
Transmit Data [31:0]. These are output concentration highway data streams with data rate options
identical to the RXD inputs.
Frame Synchronization. This signal indicates the beginning of a 125 µs frame event (8 kHz). The
FSYNC ball can be programmed as active-low or active-high, but its polarity is the same for all
concentration highway interfaces (CHI). FSYNC can be sampled on either the positive or negative
edge of CHICLK. Time-slot numbers and bit offsets for each CHI are assigned relative to the detection
of FSYNC.
Clock. This is the master synchronous clock for the transmit and receive concentration highways. The
frequency can be 8.192 MHz or 16.384 MHz. It must be at least as fast as the highest CHI data rate.
Clock Speed. Static control input that should be tied according to the frequency of CHICLK. If CHICLK
is connected to an 8.192 MHz source, CKSPD0 should be tied to V
16.384 MHz source, CKSPD0 should be tied to V
Name/Description
Name/Description
Description
DD33
.
SS
. If CHICLK is connected to a
Table 4-1 on page 18
Data Sheet, Revision 3
September 21, 2005
Agere Systems Inc.
through