TSI-2 AGERE [Agere Systems], TSI-2 Datasheet - Page 52

• Manufacturer Part Number: TSI-2
• Description: 2k x 2k Time-Slot Interchanger
• Manufacturer: AGERE [Agere Systems]

TSI-2
2k x 2k Time-Slot Interchanger
Table 6-51. Transmit_CHI_Global_Configuration (Read/Write)
52
52
Address Bit
0x00C84 15:8 Unused.
6:4 Transmit_High_Impedance_Delay. These bits are used in conjunction with Driver_Enable_Control
7
3
2
1
0
Global_Transmit_CHI_Output_Enable. This bit is a global control over the 3-state enables of
the transmit CHIs.
0 = All CHIs transmit pins are forced into the high-impedance state.
1 = 3-state control of individual CHIs is placed under control of the CHI
(see
Transmit_High_Impedance_Delay bits determine how early the device will 3-state the output driver at
the end of a time slot. These numbers are approximate because of the sampling error between the
CHICLK and the internal clock. The numbers are actually how much time after the previous clock
edge the output 3-states. For bit settings [6:4]:
000 = Approximately 55 ns after the previous same edge with a 16.384 MHz CHICLK.
001 = Approximately 49 ns after the previous same edge with a 16.384 MHz CHICLK.
010 = Approximately 43 ns after the previous same edge with a 16.384 MHz CHICLK.
011 = Approximately 37 ns after the previous same edge with a 16.384 MHz CHICLK.
100 = Approximately 116 ns after the previous same edge (8.192 MHz CHICLK only).
101 = Approximately 110 ns after the previous same edge (8.192 MHz CHICLK only).
110 = Approximately 104 ns after the previous same edge (8.192 MHz CHICLK only).
111 = Approximately 98 ns after the previous same edge (8.192 MHz CHICLK only).
See
Force_Transmit_CHI_Resynchronization.
0 = Normal operation.
1 = This forces the transmit CHI/PLL interface to resynchronize.
Enable_Transmit_CHI_Automatic_Resynchronization.
0 = The device will inhibit automatic resynchronization of the transmit CHI/PLL interface if it
1 = The device will automatically resynchronize the CHI/PLL interface if it detects it is out-of-syn-
Transmit_Frame_Sync_Polarity. This bit indicates the polarity of the frame synchronization sig-
nal.
0 = Indicates the frame synchronization is active-low. Generally, this should be programmed with
1 = Indicates the frame synchronization is active-high.
Transmit_Clock_Edge. This bit indicates which edge of the CHICLK to use to sample the frame
synchronization signal.
0 = Indicates sampling on the falling edge. Generally, this should be programmed with the same
1 = Indicates sampling on the rising edge of the clock.
Transmit_CHI_Configuration register (see
detects it is out-of-synchronization (not recommended).
chronization.
the same value as Receive_Frame_Sync_Polarity (see
ence point for all receive CHI timing is the first active edge of CHICLK (see
Transmit_Clock_Edge below) after the frame synchronization transitions to the active level as
defined here.
value as Receive_Clock_Edge (see
point for all transmit CHI timing and offsets.
= Approximately 55 ns after the previous opposite edge with an 8.192 MHz CHICLK.
= Approximately 49 ns after the previous opposite edge with an 8.192 MHz CHICLK.
= Approximately 43 ns after the previous opposite edge with an 8.192 MHz CHICLK.
= Approximately 37 ns after the previous opposite edge with an 8.192 MHz CHICLK.
Figure 5-15 on page 27
Table 6-48
bits [13:12]) bits. When the Driver_Enable_Control bits = 11, then the
and
Table 5-5 on page
Name/Description
Table 6-47 on page
Table 6-48 on page
27.
Table 6-47 on page
49). This also defines the reference
50).
Data Sheet, Revision 3
49). The refer-
September 21, 2005
Agere Systems Inc.
Defaul
000
—
0
0
0
0
0
t