TSI-2 AGERE [Agere Systems], TSI-2 Datasheet
TSI-2
Related parts for TSI-2
TSI-2 Summary of contents
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... Related Documents The documentation package for this device consists of the following documents: The TSI Time-Slot Interchanger Product Brief, the TSI Family Selection Guide, the TSI Time-Slot Interchanger Data Sheet (this document), and the TSI-2 Time-Slot Interchanger System Design Guide. ...
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... TSI Time-Slot Interchanger Contents 1 Introduction .........................................................................................................................................................................1 1.1 Related Documents .....................................................................................................................................................1 1.2 Block Diagram and High-Level Interface Definition .....................................................................................................1 2 Ball Information ...................................................................................................................................................................7 2.1 Top View Ball Diagram ................................................................................................................................................7 2.2 Package Ball Assignments ..........................................................................................................................................8 2.3 Package Ball Matrix ...................................................................................................................................................10 2.3.1 Top View ..........................................................................................................................................................10 2.3.2 Bottom View .....................................................................................................................................................11 2.4 Ball Types ..................................................................................................................................................................12 2.5 Ball Definitions ...........................................................................................................................................................12 3 Operating Conditions and Reliability ................................................................................................................................15 3.1 Absolute Maximum Ratings .......................................................................................................................................15 3 ...
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... Table 6-19. Scratch_Register (Read/Write)..........................................................................................................................38 Table 6-20. Reserved_0 (Read/Write) ..................................................................................................................................39 Table 6-21. CSG_Control (Read/Write) ................................................................................................................................39 Table 6-22. CSG_Status (Read Only)...................................................................................................................................40 Table 6-23. CSG_Starting_Address (Read/Write) ................................................................................................................40 Table 6-24. CSG_Ending_Address (Read/Write) .................................................................................................................40 Table 6-25. CSG_Write_Enable_Low (Read/Write)..............................................................................................................40 Table 6-26. CSG_Write_Enable_High (Read/Write).............................................................................................................40 Table 6-27. CSG_Seed_Low (Read/Write)...........................................................................................................................41 Table 6-28. CSG_Seed_High (Read/Write)..........................................................................................................................41 Agere Systems Inc. Table of Contents (continued) TSI Time-Slot Interchanger Page 3 ...
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... TSI Time-Slot Interchanger Tables Table 6-29. CSG_OR_Mask_Low (Read/Write) ...................................................................................................................41 Table 6-30. CSG_OR_Mask_High (Read/Write) ..................................................................................................................41 Table 6-31. CSG_AND_Mask_Low (Read/Write) .................................................................................................................42 Table 6-32. CSG_AND_Mask_High (Read/Write) ................................................................................................................42 Table 6-33. CS_Stream_Control (Read/Write) .....................................................................................................................42 Table 6-34. CSG_Configuration (Read/Write) ......................................................................................................................43 Table 6-35. TPG_Configuration (Read/Write).......................................................................................................................44 Table 6-36. TPG_User_Pattern (Read/Write) .......................................................................................................................44 Table 6-37. TPM_Configuration (Read/Write) ......................................................................................................................45 Table 6-38. TPM_User_Pattern (Read/Write).......................................................................................................................45 Table 6-39. TPM_Error_Count (Sat/Roll*) ............................................................................................................................46 Table 6-40. TPG_Inject_Error_Count (Write Only) ...............................................................................................................46 Table 6-41 ...
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... Figure 5-14. Transmit CHI Timing with 8.192 Mbits/s Data and 8.192 MHz CHICLK ..........................................................26 Figure 5-15. CHI 3-State Output Control ..............................................................................................................................27 Figure 5-16. Microprocessor Port Timing—Read Cycle .......................................................................................................28 Figure 5-17. Microprocessor Port Timing—Write Cycle .......................................................................................................29 Figure 6-1. Transmit CHI Configuration (R/W) .....................................................................................................................50 Agere Systems Inc. Table of Contents (continued) TSI Time-Slot Interchanger Page 5 ...
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... TSI Time-Slot Interchanger 6 6 Hardware Description Data Sheet, Revision 3 September 21, 2005 Agere Systems Inc. ...
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... The device is housed in a 240-ball plastic ball grid array. Figure 2-1 shows the ball arrangement viewed from the top of the package. The balls are spaced on a 1.0 mm pitch Agere Systems Inc Figure 2-1. Package Diagram (Top View Time-Slot Interchanger TSI-2 7 ...
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... TSI Time-Slot Interchanger 2.2 Package Ball Assignments Table 2-1. Package Ball Assignments in Signal Name Order Symbol Ball Symbol ADDR00 A17 DATA13 ADDR01 A16 DATA14 ADDR02 A15 DATA15 ADDR03 A14 DT ADDR04 A13 FSYNC ADDR05 A12 HIZ ADDR06 A11 INT ADDR07 A10 MPUCLK ADDR08 ...
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... R15 D15 B14 L15 R13 V SSPLL TSI-2 Ball B3 C15 J15 R10 B8 D11 K11 T16 B13 H8 L11 V18 ...
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... TSI Time-Slot Interchanger 2.3 Package Ball Matrix 2.3.1 Top View Table 2-2. Package Ball Assignments (Top View ADDR15 ADDR14 ADDR13 ADDR12 TXD00 TXD02 TXD01 DD15 TXD04 TXD03 DD15 TXD06 TXD05 — ...
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... DD15 DD15 DD15 DD15 DD15 DD15 ADDR05 ADDR04 ADDR03 ADDR02 ADDR01 TSI RSV11 V SS VSS V SS VSS VDD33 RSV10 PAR0 HIZ DATA14 DATA13 DATA10 DATA09 DATA06 DATA05 DATA03 DATA02 DATA01 DATA00 AS R/W CS ...
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... TSI Time-Slot Interchanger 2.4 Ball Types This table describes each type of input, output, and I/O ball used in the device. Table 2-4. Ball Types Type Label I CMOS input, TTL switching thresholds CMOS input, TTL switching thresholds with internal pull-down resistor CMOS input, TTL switching thresholds with internal pull-up resistor. ...
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... I pu Output Enable. All output and bidrectional buffers will be high-impedance when this input is low unless HIZ boundary scan is enabled (TRSTN = 1). 20 kΩ pull-up resistor. RSV[11:1] — Reserved [11:1]. These balls are used by Agere Systems during the manufacturing process; they must be left unconnected. Agere Systems Inc Time-Slot Interchanger Name/Description Name/Description TSI-2 13 ...
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... TSI Time-Slot Interchanger Table 2-9. Power Balls Symbol Type V P I/O Power. Power supply balls for the I/O pads (3.3 V ± 5%). DD33 V P Core Power. Power supply balls for the core (1.5 V ± 5%). DD15 V P Ground. Common ground balls for 3.3 V and 1.5 V supplies PLL Power. 1.5 V power supply for the internal phase-locked loop. Must include local 0.01 µF capacitor to ...
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... TSI-2 Agere Systems Inc Time-Slot Interchanger Min Max –0.5 –0.5 –0.5 –0.3 V DD33 –40 — Min Typ 3.14 3.3 1.4 1.5 –40 — Voltage 2,000 V 500 V TSI-2 Unit 4.2 V 1 0.3 V 125 °C 125 °C Max Unit 3. °C Type HBM (human-body model) CDM (charged-device model) ...
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... TSI Time-Slot Interchanger 3.4 Thermal Parameters (Definitions and Values) System and circuit board level performance depends not only on device electrical characteristics, but also on device thermal characteristics. The thermal characteristics frequently determine the limits of circuit board or system performance, and they can be a major cost adder or cost avoidance factor. When the die temperature is kept below 125 °C, temperature-activated failure mechanisms are minimized ...
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... Power Consumption Table 3-5. Power Consumption Supply Voltage V DD33 V DD15 * MPUCLK = 66 MHz, CHICLK = 16.384 MHz °C, all CHIs active, all outputs loaded with 50 pF. Agere Systems Inc Time-Slot Interchanger * Typ 100 mW at 3.3 V 275 mW at 1.5 V TSI-2 Max 150 mW at 3.47 V 325 ...
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... TSI Time-Slot Interchanger 4 dc Electrical Characteristics This section describes all the static parameters associated with all the ball types used in the device. Table 4-1. CMOS Inputs Parameter Symbol Input Leakage Current High-input Voltage Low-input Voltage Input Capacitance * Excludes current due to pull-up or pull-down resistors. ...
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... V DD33 Figure 5-2. MPUCLK Timing Specifications Min — 6.06 — 15 Time-Slot Interchanger 50% Typ Max 2 7 — 73.24 — 36. 122.07 — 61.03 — 50% Typ Max 2 7 — — — — TSI-2 Unit Unit ...
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... TSI Time-Slot Interchanger Figure 5-3 shows the ac timing specifications for the Table 5-3. CMOS Output ac Timing Specification * Parameter Description t Rise Time (20%—80 Fall Time (80%—20 Test load = 50 pF (total CMOS outputs on the device 20% t9 Figure 5-3. ac Timing Specification Min Typ — ...
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... At all RXD and TXD rates (16.384 Mbits/s, 8.192 Mbits/s, 4.096 Mbits/s, or 2.048 Mbits/s) with a CHICLK frequency of 16.384 MHz or 8.192 MHz. Agere Systems Inc Figure 5-4. CHI Interface Timing Description Figure 5-15, CHI 3-State Output Control on page TSI Time-Slot Interchanger Min Max Unit 10 — — ...
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... TSI Time-Slot Interchanger FSYNC CHICLK w/ 0 offset TS255 B6 w/ ¼ bit offset TS255 B6 w/ ½ bit offset TS255 B6 w/ ¾ bit offset TS255 B5 TS255 B6 w/ bit offset = 1 TS255 B5 w/ 2¾ bit offset TS255 B3 TS255 B4 w/ bit offset = 7 TS254 offset = 1, ...
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... TS0 B3 TS0 B4 TS0 B2 TS0 B3 TS0 B2 TS0 B3 TS0 B2 TS0 B3 TS0 B1 TS0 B2 TS0 B3 TS0 B0 TS0 B1 TS127 B3 TS127 B4 TS127 B5 TS127 B2 TS127 B3 TS127 B4 TS114 B7 TS115 B0 TS0 B3 TS0 B4 TS0 B2 TS0 B3 TS0 B1 TS0 B2 TS0 B3 TS0 B1 TS0 B2 TS0 B1 TS0 B2 TS127 B2 TS127 B3 TS0 B2 TS0 B3 TSI-2 TS0 B4 TS115 B1 TS0 B3 23 ...
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... TSI Time-Slot Interchanger FSYNC CHICLK w/ 0 offset w/ ¼ bit offset TS63 B7 w/ ½ bit offset TS63 B7 w/ ¾ bit offset TS63 B7 w/ bit offset = 1 w/ 2¾ bit offset TS63 B5 w/ bit offset = offset = 1, bit offset = offset = 13, TS50 B4 bit offset = 3¼ ...
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... TS31 B7 TS31 B7 TS0 Time-Slot Interchanger TS0 B1 TS0 B1 TS0 B1 data sampled TS0 B0 data sampled TS0 B0 TS31 B6 data sampled TS31 B2 TS31 B1 TS18 B6 TS0 B1 data sampled TS0 B0 TS0 B0 TS0 B0 TS31 B7 TS31 B0 TS0 B1 TSI-2 TS0 TS31 TS0 TS0 B1 TS0 B0 TS31 B01 25 ...
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... TSI Time-Slot Interchanger FSYNC CHICLK w/ 0 offset TS127 B6 w/ ¼ bit offset TS127 B6 w/ ½ bit offset TS127 B6 w/ ¾ bit offset TS127 B5 TS127 B6 w/ bit offset = 1 TS127 B5 w/ 2¾ bit offset TS127 B3 TS127 B4 w/ bit offset = 7 TS126 offset = 1, ...
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... Like edge is the reference edge (rising or falling) as defined by bit 0 in Agere Systems Inc Figure 5-15. CHI 3-State Output Control Table 6-51 Transmit_CHI_Global_Configuration (Read/Write) on page Table 6-48 Transmit_CHI_Configuration (Read/Write Reference Point Table 6-51 Transmit_CHI_Global_Configuration (Read/Write) on page TSI Time-Slot Interchanger * Min Max Unit ...
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... TSI Time-Slot Interchanger MPUCLK t ADDR[15: R/W DATA[15:0] PAR[1: Figure 5-16. Microprocessor Port Timing—Read Cycle Table 5-6. Microprocessor Port Timing—Read Cycle Parameter t Address Setup 23 Address Hold t 24 Chip Select Setup t 25 Chip Select Hold t 26 Address Strobe Setup t 27 ...
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... Figure 5-17 on page Time-Slot Interchanger Min Max 5 — 1 — 5 — 1 — 5 — 1 — 5 — 1 — 5 — 1 — and Table 5-7 on page 29. A posted write may TSI-2 Unit ...
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... TSI Time-Slot Interchanger 30 30 Register Description Data Sheet, Revision 3 September 21, 2005 Agere Systems Inc. ...
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... Address Space (Words) 512 256 256 256 896 1,920 4,096 24,576 16,364 16,324 TSI Time-Slot Interchanger Address Range 0x00000—0x003FE 0x00400—0x005FE 0x00600—0x007FE 0x00800—0x009FE 0x00A00—0x010FE 0x01100—0x01FFE 0x02000—0x03FFE 0x04000—0x0FFFE 0x10000—0x17FFE 0x18000—0x1FFFE ...
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... TSI Time-Slot Interchanger 6.4 Register Summary Table 6-2. Global Registers Address 0x00000 Version_Control 0x00002 Chip_Identity 0x00004 Summary_Interrupt_Status 0x00006 Summary_Interrupt_Mask 0x00008 CPU_Access_Error 0x0000A CPU_Access_Error_Mask 0x0000C Global_Control 0x0000E PLL_Control 0x00010 Power_Control 0x00012 Invalid_Address_Trap 0x00014 Scratch_Register * Clear-on-read/clear-on-write. Table 6-3. Connection Store Generator Registers Address ...
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... Data_Store_Time_Slot_Capture_Select 0x01144 Data_Store_Captured_Data 0x01146 Connection_Store_Parity_Error_Address_Trap 0x01148 Receive_Link_Offset 0x0114C Transmit_Link_Offset 0x0114E Wide_Mode_Control * Clear-on-read/clear-on-write. Agere Systems Inc. Register Register Register TSI Time-Slot Interchanger Access Mode Read/Write Read/Write Read/Write Read/Write * Sat/Roll Write Only Read/Write Read Only Read/Write Access Mode Read/Write * CORWN ...
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... TSI Time-Slot Interchanger Table 6-7. Connection Store Address 0x10000—0x17FFC Low_Control_Word 0x10002—0x17FFE High_Control_Word Table 6-8. Reserved Registers The following register will not cause an Invalid_Address_Error (see Address 0x00016 Reserved_0 6.5 Global Control Registers The default field indicates the state of each register bit following a hardware or software reset cycle. ...
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... The CPU_Access_Interrupt bit (see Table 6-11) will cause an interrupt if active The CPU_Access_Interrupt bit is blocked from causing an interrupt. Agere Systems Inc. Name/Description Table 6-49 on page Table 6-45 on page Table 6-42 on page 47). 54). Table 6-13 on page Name/Description Time-Slot Interchanger Default 51). 48). 36). Default TSI-2 — — — — — — — — — ...
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... TSI Time-Slot Interchanger Table 6-13. CPU_Access_Error (CORWN) Address Bit 0x00008 15:4 Unused. 3 PLL_Lock_Error. This bit indicates if the device's master PLL is locked to the incoming CHI reference clock (CHICLK Locked Not locked. 2 Access_Time_Out_Error time-out Indicates that a time-out has occurred internal to the TFRA84J13 device on a microprocessor access ...
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... Register_Clearing_Mode. This bit controls the way clearing is performed on status bits in clear- on-read/clear-on-write registers The status bit is cleared by writing it The status bit is cleared when a microprocessor read is performed. Agere Systems Inc Time-Slot Interchanger Name/Description TSI-2 Default 0 — — — 1 ...
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... TSI Time-Slot Interchanger Table 6-16. PLL_Control (Read/Write) This register provides control over the PLL filter parameters. This register is unaffected by software reset. Address Bit 0x0000E 15:11 Unused. 10 Reserved. 9:7 Loop_Filter_Resistor. These bits provide loop filter resistor control over the PLL. The loop filter damping resistor is approximately (Loop_Filter_Resistor + 1) x (20 kΩ). This field is only enabled if Enable_PLL_Control is set ...
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... Note: During the CSG operation, the function of the switch fabric is halted and the outputs of the CHIs and HSLs are nondeterministic. To reuse the CSG for subsequent programming of the connection store, this bit must be set back to 0 then Agere Systems Inc Time-Slot Interchanger Name/Description Name/Description Table 6-33 on page TSI-2 Default — — — Default — 0 ...
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... TSI Time-Slot Interchanger Table 6-22. CSG_Status (Read Only) This register provides general status of the connection store generator. Address Bit 0x00402 15:1 Unused. 0 CSG_Operation_Complete. Pattern generation for connection and data store is complete. The bit is normally asserted, but it is deasserted when the CSG update is in progress. This status bit is cleared when the CSG_Enable bit (see 0 = Pattern generator is busy ...
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... The result- ant is then ANDed with CSG_AND_Mask_High. Agere Systems Inc Time-Slot Interchanger Name/Description Table 6-21 on page Name/Description Table 6-21) is asserted, at the begin- Name/Description Name/Description TSI-2 Default 39) is asserted, at 0xFFFF Default — 0x7FFF Default 0x0000 Default 0x000 — ...
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... TSI Time-Slot Interchanger Table 6-31. CSG_AND_Mask_Low (Read/Write) This register allows bits in the connection store to be forced to 0. This register takes precedence over CSG_OR_Mask_Low. CS[15:0] = (pseudorandom data [15:0] OR CSG_OR_Mask_Low) AND CSG_AND_Mask_Low, bit enabled by CSG_Write_Enable_Low. Address Bit 0x0041C 15:0 CSG_AND_Mask_Low. This register allows bit fields in the connection store to be forced during a CSG fill operation ...
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... Frame integrity Alternate data TGP data. 7 High_Impedance_Control_Field_Fill. Fills the Time_Slot_High_Impedance control bit (see Table 8-2) in the connection store. 6:0 Unused. Agere Systems Inc Time-Slot Interchanger Table 6-21 on page 39 Name/Description Table 8-2) in the connection store are filled TSI-2 bit 1). Default 00000 Table 8 — 43 ...
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... TSI Time-Slot Interchanger 6.7 Test Pattern Generator and Monitor Registers Table 6-35. TPG_Configuration (Read/Write) The TPG can be configured to generate any one of the ITU-T test patterns specified in O.150, O.151, or O.152, as well as idle code or user-specified data. Address Bit 0x00600 15:7 Unused. 6 TPG_Pattern_Invert. Data output patterns are inverted when this bit is selected. ...
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... TPM_Pattern_Select field, this data will be used to check against incoming data. Bit [15] gets checked first in time. Agere Systems Inc. Name/Description 20 – 1 with zero suppression when the next 14 bits are zero). 20 – 1 with zero suppression when the next 14 bits are zero). Name/Description TSI Time-Slot Interchanger Default — Table 6-39 0x0 Default 0x0000 0 ...
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... TSI Time-Slot Interchanger Table 6-39. TPM_Error_Count (Sat/Roll*) Address Bit 0x00608 15:0 TPM_Error_Count. This status register accumulates the number of pattern bit errors detected in the monitored time slot(s). If Saturate_Rollover_Select (see urate at 0xFFFF and not be allowed to roll over. If Saturate_Rollover_Select is set the counter will roll over (count to 0x0 on the next error after 0XFFFF), the Pattern_Error_Detected status bit (see will not be reset ...
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... Masked. An error will not cause an interrupt. 0 Pattern_Error_Mask. This bit masks the Pattern_Error_Detected bit (see Table 6-42) from causing an interrupt Nonmasked. An error will cause an interrupt Masked. An error will not cause an interrupt. Agere Systems Inc. Name/Description 46) is nonzero. Name/Description TSI Time-Slot Interchanger Default — — — Default — ...
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... TSI Time-Slot Interchanger 6.8 Concentration Highway Configuration Registers Table 6-44. Receive_CHI_Configuration (Read/Write) Each of the incoming CHIs can be independently designed and programmed with a unique offset from the master frame synchronization. This bank of registers works in conjunction with the corresponding Receive_CHI_Time_Slot_Offset regis- ters (see Table 6-52 on page 53) to provide this control ...
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... Indicates sampling on the rising edge of the clock. Agere Systems Inc Time-Slot Interchanger Table 6-45). Name/Description Table 6-45) will cause an interrupt if active (unless Table 6-45) will cause an interrupt if active (unless Table 6-45) will cause an interrupt if active Name/Description TSI-2 Default — Default — ...
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... TSI Time-Slot Interchanger Table 6-48. Transmit_CHI_Configuration (Read/Write) Each of the incoming CHIs can be independently designed and programmed with a unique offset from the master frame synchronization. This bank of registers works in conjunction with the corresponding Transmit_CHI_Time_Slot_Offset regis- ters (see Table 6-53 on page 53) to provide this control. These registers provide the bit and fractional bit offset control. ...
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... The Transmit_Frame_Sync_Error bit (see Table 6-49) will cause an interrupt if active (unless masked at a higher level The Transmit_Frame_Sync_Error bit is blocked from causing an interrupt. Agere Systems Inc. Name/Description 52), then a manual resynchronization should be performed Table 6-51). Name/Description TSI Time-Slot Interchanger Default — — — Default — 1 ...
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... TSI Time-Slot Interchanger Table 6-51. Transmit_CHI_Global_Configuration (Read/Write) Address Bit 0x00C84 15:8 Unused. 7 Global_Transmit_CHI_Output_Enable. This bit is a global control over the 3-state enables of the transmit CHIs All CHIs transmit pins are forced into the high-impedance state 3-state control of individual CHIs is placed under control of the CHI Transmit_CHI_Configuration register (see 6:4 Transmit_High_Impedance_Delay ...
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... Name/Description CHI Rate Offset 16 Mbits/s TTO (0—255) 8 Mbits/s TTO (0—127) 4 Mbits/s TTO (0—63) 2 Mbits/s TTO (0—31) TSI Time-Slot Interchanger Default RC_TS_OFF Value RTO ((RTO modulo 256 ((RTO modulo 256 ((RTO 14) modulo 256 Default — — TC_TS_OFF Value ...
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... TSI Time-Slot Interchanger 7 Switch Fabric Control Table 7-1. SF_Status (CORWN) Address Bit 0x01124 15:3 Unused. 2 Receive_Link_Synchronization_Error error detected Missing or misplaced synchronization on interface between the receive CHI and the switch fabric (clear-on-read/clear-on-write). 1 Transmit_Sync_Error error detected Missing or misplaced synchronization on interface between the transmit CHI and the switch fabric (clear-on-read/clear-on-write) ...
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... Data_Store_Time_Slot_Capture (see Table 7-3). This field is updated every other frame alternating with Captured_Data_1. Depending on when this is read by the microprocessor, it may be either from the frame before or after that sampled in Captured_Data_1. Agere Systems Inc Time-Slot Interchanger Name/Description Name/Description TSI-2 Default — 0x0000 Default — — ...
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... TSI Time-Slot Interchanger Table 7-5. Connection_Store_Parity_Error_Address_Trap (CORWN) As the connection store is continually read, its parity is checked error is detected, the location with the error is saved in this register and the Connection_Store_Parity_Error (see mode, when this register is read, the Connection_Store_Parity_Error bit is cleared clear-on-write (COW) mode, any write to this register clears Connection_Store_Parity_Error ...
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... LL mode will µs, 15 µs, and 31 µs larger, and the maximum delay will 132 µs, 140 µs, and 156 µs larger than regular mode. Agere Systems Inc Time-Slot Interchanger Name/Description TSI-2 Default — 000 57 ...
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... TSI Time-Slot Interchanger 8 Connection Store The connection store RAM contains the per-time-slot control information for outgoing time slots. Each location in the RAM corresponds to one outgoing time slot and contains all the time-slot specific control information for that time slot. The specific address offset into the RAM is calculated as follows: ADDR[15 ...
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... Alternate data TPG data. 7 Reserved. Note: This bit must be set to zero. 6:5 Unused. 4 General_Purpose_Bit. This is a general-purpose read/write bit. It causes no action within the device. 3:0 Unused. Agere Systems Inc. Name/Description checking. TSI Time-Slot Interchanger Default 0x0 — — — — — — 59 ...
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... TSI Time-Slot Interchanger 9 Outline Diagrams Note: Dimensions are in millimeters. A1 INDICATOR (PLATED) 0.80 ± 0.050 0.56 ± 0.06 18 1.00 TYP 0. TOP VIEW 19.00 SQUARE +0.70 17.70 –0.05 SQUARE 30° APPROX ALL SIDES 0.50 R MAX ALL EDGES +0.07 0.63 DIA –0.13 BOTTOM VIEW Data Sheet, Revision 3 September 21, 2005 1 ...
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... Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Agere, Agere Systems, and the Agere logo are registered trademarks of Agere Systems Inc. Copyright © 2005 Agere Systems Inc. All Rights Reserved September 21, 2005 DS05-116STSI-3 (Replaces DS05-116STSI-2) Ball Count 240 5-6. 5-7. ...