MT46V16M8TG-8L MICRON [Micron Technology], MT46V16M8TG-8L Datasheet - Page 62

• Manufacturer Part Number: MT46V16M8TG-8L
• Description: DOUBLE DATA RATE DDR SDRAM
• Manufacturer: MICRON [Micron Technology]

TIMING PARAMETERS
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
SYMBOL
t
t
t
t
t
CH
CL
CK (2.5)
CK (2)
IH
COMMAND
ADDR
CKE
DQS
MIN
CK#
DM
0.45
CK
NOTE: 1. Clock must be stable before exiting self refresh mode. That is, the clock must be cycling within
DQ
7.5
7.5
1
1
1
4
-75Z
MAX
0.55
0.45
2. Device must be in the all banks idle state prior to entering self refresh mode.
3.
4. AR = AUTO REFRESH command.
13
13
specifications by Ta0.
t
is required before a READ command can be applied.
t
t
XSNR is required before any non-READ command can be applied, and
IS
IS
t
0.550.45
NOP
RP
T0
MIN
0.45
7.5
10
1
t
2
t
IH
IH
t
CH
-75
MAX
0.55
0.55
13
13
t
CL
t
IS
MIN
0.45
0.45
1.1
10
AR
8
T1
Enter Self Refresh Mode
-8
MAX
0.55
0.55
SELF REFRESH MODE
13
13
UNITS
t
t
ns
ns
ns
CK
CK
(
(
(
(
(
(
(
(
)
(
)
(
)
(
)
(
)
(
)
)
)
)
)
)
)
)
62
(
(
(
(
(
(
(
(
)
(
)
(
)
(
)
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)
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)
)
)
)
)
SYMBOL
t
t
t
t
IS
RP
XSNR
XSRD
Ta0
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MIN
200
20
75
1
1
t CK
-75Z
MAX
t IS
128Mb: x4, x8, x16
NOP
Ta1
MIN
Exit Self Refresh Mode
200
20
75
1
t
XSRD (200 cycles of CK)
-75
t XSNR/
t XSRD
MAX
(
(
(
(
(
(
(
)
)
)
)
)
)
)
(
(
(
(
(
(
(
)
)
)
)
)
)
)
(
(
(
(
(
(
(
)
)
)
)
)
)
)
(
(
(
(
(
(
(
)
)
)
)
)
)
)
DDR SDRAM
3
t IS
PRELIMINARY
MIN
VALID
VALID
200
1.1
Tb0
20
80
DON’T CARE
©2001, Micron Technology, Inc.
-8
t IH
MAX
UNITS
t
ns
ns
ns
CK