MT46V16M8TG-8L MICRON [Micron Technology], MT46V16M8TG-8L Datasheet - Page 26

• Manufacturer Part Number: MT46V16M8TG-8L
• Description: DOUBLE DATA RATE DDR SDRAM
• Manufacturer: MICRON [Micron Technology]

WRITES
mand, as shown in Figure 14.
vided with the WRITE command, and auto precharge
is either enabled or disabled for that access. If auto
precharge is enabled, the row being accessed is
precharged at the completion of the burst. For the
generic WRITE commands used in the following illus-
trations, auto precharge is disabled.
will be registered on the first rising edge of DQS follow-
ing the WRITE command, and subsequent data ele-
ments will be registered on successive edges of DQS. The
LOW state on DQS between the WRITE command and
the first rising edge is known as the write preamble; the
LOW state on DQS following the last data-in element
is known as the write postamble.
first corresponding rising edge of DQS (
specified with a relatively wide range (from 75 percent
to 125 percent of one clock cycle). All of the WRITE
diagrams show the nominal case, and where the two
extreme cases (i.e.,
might not be intuitive, they have also been included.
Figure 15 shows the nominal case and the extremes of
t
assuming no other commands have been initiated, the
DQs will remain High-Z and any additional input data
will be ignored.
with or truncated with a subsequent WRITE com-
mand. In either case, a continuous flow of input data
can be maintained. The new WRITE command can be
issued on any positive edge of clock following the
previous WRITE command. The first data element
from the new burst is applied after either the last
element of a completed burst or the last desired data
element of a longer burst which is being truncated. The
new WRITE command should be issued x cycles after
the first WRITE command, where x equals the number
of desired data element pairs (pairs are required by the
2n-prefetch architecture).
ample of nonconsecutive WRITEs is shown in Figure
17. Full-speed random write accesses within a page or
pages can be performed as shown in Figure 18.
subsequent READ command. To follow a WRITE with-
out truncating the WRITE burst,
as shown in Figure 19.
subsequent READ command, as shown in Figure 20.
Note that only the data-in pairs that are registered
prior to the
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
DQSS for a burst of 4. Upon completion of a burst,
WRITE bursts are initiated with a WRITE com-
The starting column and bank addresses are pro-
During WRITE bursts, the first valid data-in element
The time between the WRITE command and the
Data for any WRITE burst may be concatenated
Figure 16 shows concatenated bursts of 4. An ex-
Data for any WRITE burst may be followed by a
Data for any WRITE burst may be truncated by a
t
WTR period are written to the internal
t
DQSS [MIN] and
t
WTR should be met
t
DQSS [MAX])
t
DQSS) is
26
array, and any subsequent data-in should be masked
with DM as shown in Figure 21.
subsequent PRECHARGE command. To follow a
WRITE without truncating the WRITE burst,
should be met as shown in Figure 22.
subsequent PRECHARGE command, as shown in Fig-
ures 23 and 24. Note that only the data-in pairs that are
registered prior to the
internal array, and any subsequent data-in should be
masked with DM as shown in Figures 23 and 24. After
the PRECHARGE command, a subsequent command
to the same bank cannot be issued until
Data for any WRITE burst may be followed by a
Data for any WRITE burst may be truncated by a
x4: A0–A9, A11
x16: A9, A11
CA = Column Address
BA = Bank Address
EN AP = Enable Auto Precharge
DIS AP = Disable Auto Precharge
x16: A0–A8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
x8: A0–A9
BA0,1
CAS#
RAS#
WE#
x8: A11
A10
CKE
CK#
CS#
CK
WRITE Command
Figure 14
128Mb: x4, x8, x16
HIGH
t
WR period are written to the
DON’T CARE
DIS AP
EN AP
BA
CA
DDR SDRAM
PRELIMINARY
©2001, Micron Technology, Inc.
t
RP is met.
t
WR