MT46V16M8TG-8L MICRON [Micron Technology], MT46V16M8TG-8L Datasheet - Page 59

• Manufacturer Part Number: MT46V16M8TG-8L
• Description: DOUBLE DATA RATE DDR SDRAM
• Manufacturer: MICRON [Micron Technology]

TIMING PARAMETERS
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
COMMAND
NOTE:
SYMBOL
t
t
t
t
t
CH
CL
CK (2.5)
CK (2)
IH
BA0, BA1
A0-A9,
V
A11
DQS
CK#
CKE
A10
V
V
DD
DM
V
DQ
CK
TT
REF
DD
66 6
Q
1
1. V
2. Reset the DLL with A8 = H.
3. t MRD is required before any command can be applied, and 200 cycles of CK are required before a READ command can be issued.
4. The two AUTO REFRESH commands at Tc0 and Td0 may be applied prior to the LOAD MODE REGISTER (LMR) command at Ta0.
5. Although not required by the Micron device, JEDEC specifies issuing another LMR command (A8 = L) prior to activating any bank.
6. PRE = PRECHARGE command, LMR = LOAD MODE REGISTER command, AR = AUTO REFRESH command, ACT = ACTIVE command, RA = Row
V
V
Address, BA = Bank Address
t
TT
DD
DD
MIN
0.45
0.45
VTD
7.5
7.5
1
Q
/V
is not applied directly to the device; however, t VTD should be greater than or equal to zero to avoid device latch-up.
,
-75Z
1
DD
V
TT,
Q are 0 volts, provided a minimum of 42 ohms of series resistance is used between the V
MAX
0.55
0.55
and V
13
13
LVCMOS
LOW LEVEL
T = 200µs
Power-up: V
REF,
MIN
0.45
0.45
7.5
10
must be equal to or less than V
1
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-75
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DD
MAX
and CK stable
0.55
0.55
t IS
t
13
13
INITIALIZE AND LOAD MODE REGISTERS
IS
T0
NOP
High-Z
High-Z
t IH
t
IH
t
CH
t
CK
MIN
0.45
0.45
1.1
10
8
t
CL
-8
ALL BANKS
t IS
PRE
MAX
T1
0.55
0.55
13
13
t IH
DD
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t RP
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Load Extended
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Mode Register
UNITS
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+ 0.3V. Alternatively, V
t
t
ns
ns
ns
CK
CK
t IS
t IS
t IS
BA0 = H,
BA1 = L
CODE
CODE
LMR
T2
t IH
t IH
t IH
59
t MRD
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Load Mode
Register
SYMBOL
t
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t
t
t
BA0 = L,
BA1 = L
IS
MRD
RFC
RP
VTD
CODE
CODE
Ta0
LMR
2
t MRD
TT
may be 1.35V maximum during power up, even if
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
ALL BANKS
MIN
t
IS
15
75
20
1
0
Tb0
PRE
200 cycles of CK
-75Z
t
IH
t RP
MAX
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TT
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128Mb: x4, x8, x16
supply and the input pin.
MIN
Tc0
3
AR
15
75
20
1
0
-75
t RFC
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DDR SDRAM
Td0
AR
PRELIMINARY
MIN
1.1
16
80
20
0
t RFC
©2001, Micron Technology, Inc.
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-8
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5
MAX
ACT 5
Te0
RA
DON’T CARE
RA
BA
UNITS
ns
ns
ns
ns
ns