MT46V16M8TG-8L MICRON [Micron Technology], MT46V16M8TG-8L Datasheet - Page 22

• Manufacturer Part Number: MT46V16M8TG-8L
• Description: DOUBLE DATA RATE DDR SDRAM
• Manufacturer: MICRON [Micron Technology]

READs (continued)
a BURST TERMINATE command, as shown in Figure
11. The BURST TERMINATE latency is equal to the
READ (CAS) latency, i.e., the BURST TERMINATE
command should be issued x cycles after the READ
command, where x equals the number of desired data
element pairs (pairs are required by the 2n-prefetch
architecture).
truncated before a subsequent WRITE command can
be issued. If truncation is necessary, the BURST TERMI-
NATE command must be used, as shown in Figure 12.
The
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
Data from any READ burst may be truncated with
Data from any READ burst must be completed or
t
DQSS (MIN) case is shown; the
t
DQSS (MAX) case
22
has a longer bus idle time. (
[MAX] are defined in the section on WRITEs.)
with, a PRECHARGE command to the same bank
provided that auto precharge was not activated. The
PRECHARGE command should be issued x cycles after
the READ command, where x equals the number of
desired data element pairs (pairs are required by the 2n-
prefetch architecture). This is shown in Figure 13.
Following the PRECHARGE command, a subsequent
command to the same bank cannot be issued until
is met. Note that part of the row precharge time is
hidden during the access of the last data elements.
A READ burst may be followed by, or truncated
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mb: x4, x8, x16
t
DQSS [MIN] and
DDR SDRAM
PRELIMINARY
©2001, Micron Technology, Inc.
t
DQSS
t
RP