MT46V16M8TG-8L MICRON [Micron Technology], MT46V16M8TG-8L Datasheet - Page 58

• Manufacturer Part Number: MT46V16M8TG-8L
• Description: DOUBLE DATA RATE DDR SDRAM
• Manufacturer: MICRON [Micron Technology]

128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
DQS, or LDQS/UDQS
DQ (Last data valid)
DQ (First data valid)
All DQs collectively
CK#
CK
3
2
DQS
CK#
DM
NOTE: 1. t DQSCK is the DQS output window relative to CK and is the“long term” component of DQS skew.
DQ
T0
CK
7
2. DQs transitioning after DQS transition define t DQSQ window.
3. All DQs must transition by t DQSQ after DQS transitions, regardless of t AC.
4. t AC is the DQ output window relative to CK, and is the“long term” component of DQ skew.
5. t LZ
6. t HZ
7. READ command with CL = 2 issued at T0.
NOTE: 1. t DSH
t LZ
(MIN)
t WPRES
(MIN)
Data Output Timing –
(MAX
T0
2. t DSS
t DQSS
T1
and t AC
,and t AC
t WPRE
(MIN)
t RPRE
t LZ
(MIN)
(MIN)
t DS
(MAX)
(MIN)
Data Input Timing
generally occurs during t DQSS
are the first valid signal transition.
generally occurs during t DQSS
are the latest valid signal transition.
T1
DI
b
T2
Figure 30
Figure 31
t DQSCK
DON’T CARE
t DSH 1
t DQSCK
T2
T2
T2
t DH
58
T1n
T2n
1
1
(MAX)
t DQSL
(MIN)
t DSS 2
T2n
T2n
T2n
t
AC and
t AC
T3
T2
4
(MIN)
t DQSH
t DSH 1
T3
T3
T3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T3n
TRANSITIONING DATA
t
T2n
DQSCK
T3n
t WPST
T3n
T3n
t AC
t DSS 2
(MAX)
(MIN)
4
T4
(MAX)
128Mb: x4, x8, x16
.
.
T3
T4
T4
T4
T4n
t DQSCK
t DQSCK
T4n
T4n
T4n
DDR SDRAM
T5
PRELIMINARY
1
1
(MAX)
(MIN)
T5
T5
T5
©2001, Micron Technology, Inc.
t HZ
T5n
t HZ
(MAX)
t RPST
(MAX)
T5n
T5n
T5n
T6