MT46V16M8TG-8L MICRON [Micron Technology], MT46V16M8TG-8L Datasheet - Page 32

• Manufacturer Part Number: MT46V16M8TG-8L
• Description: DOUBLE DATA RATE DDR SDRAM
• Manufacturer: MICRON [Micron Technology]

128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
COMMAND
ADDRESS
t
t
t
DQSS (NOM)
DQSS (MIN)
DQSS (MAX)
DQS
DQS
DQS
NOTE: 1. DI b = data-in for column b.
CK#
DM
DM
DM
DQ
DQ
DQ
CK
2. An interrupted burst of 4 or 8 is shown; two data elements are written.
3. One subsequent element of data-in is applied in the programmed order following DI b.
4. t WTR is referenced from the first positive CK edge after the last data-in pair.
5. A10 is LOW with the WRITE command (auto precharge is disabled).
6. DQS is required at T2 and T2n (nominal case) to register DM.
7. If the burst of 8 was used, DM would not be required at T3 -T4n because the READ command would
mask the last two data elements.
Bank a,
WRITE
Col b
T0
t
t
t
DQSS
DQSS
DQSS
DI
b
NOP
T1
DI
b
WRITE to READ – Interrupting
DI
b
T1n
NOP
T2
Figure 20
t
WTR
32
T2n
Bank a,
READ
Col n
T3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DON’T CARE
CL = 2
CL = 2
CL = 2
T4
NOP
128Mb: x4, x8, x16
TRANSITIONING DATA
DDR SDRAM
T5
NOP
PRELIMINARY
DI
DI
DI
n
n
n
©2001, Micron Technology, Inc.
T5n
T6
NOP