MT46V16M8TG-8L MICRON [Micron Technology], MT46V16M8TG-8L Datasheet - Page 42

• Manufacturer Part Number: MT46V16M8TG-8L
• Description: DOUBLE DATA RATE DDR SDRAM
• Manufacturer: MICRON [Micron Technology]

NOTE (continued):
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
3. Current state definitions:
4. AUTO REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge
8. Requires appropriate DM masking.
9. A WRITE command may be applied after the completion of the READ burst; otherwise, a BURST TERMI-
the current state only.
enabled and READs or WRITEs with auto precharge disabled.
NATE must be used to end the READ burst prior to asserting a WRITE command.
Precharge Enabled: See following text – 3a
Precharge Enabled: See following text – 3a
3a. The READ with auto precharge enabled or WRITE with auto precharge enabled states can each be
Read with Auto
Write with Auto
broken into two parts: the access period and the precharge period. For read with auto precharge,
the precharge period is defined as if the same burst was executed with auto precharge disabled and
then followed with the earliest possible PRECHARGE command that still accesses all of the data in
the burst. For WRITE with auto precharge, the precharge period begins when
measured as if auto precharge was disabled. The access period starts with registration of the
command and ends where the precharge period (or
During the precharge period of the READ with auto precharge enabled or WRITE with auto
precharge enabled states, ACTIVE, PRECHARGE, READ, and WRITE commands to the other bank may
be applied; during the access period, only ACTIVE and PRECHARGE commands to the other bank
may be applied. In either case, all other related limitations apply (e.g., contention between read
data and write data must be avoided).
This means concurrent auto precharge is not supported.
Row Active: A row in the bank has been activated, and
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet
Idle: The bank has been precharged, and
and no register accesses are in progress.
terminated or been terminated.
terminated or been terminated.
42
t
RP has been met.
t
RP) begins.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RCD has been met. No data bursts/accesses
128Mb: x4, x8, x16
t
WR ends, with
DDR SDRAM
PRELIMINARY
©2001, Micron Technology, Inc.
t
WR