MT46V16M8TG-8L MICRON [Micron Technology], MT46V16M8TG-8L Datasheet - Page 10

• Manufacturer Part Number: MT46V16M8TG-8L
• Description: DOUBLE DATA RATE DDR SDRAM
• Manufacturer: MICRON [Micron Technology]

operation or incompatibility with future versions may
result.
block of columns equal to the burst length is effectively
selected. All accesses for that burst take place within this
block, meaning that the burst will wrap within the
block if a boundary is reached. The block is uniquely
selected by A1-Ai when the burst length is set to two, by
A2-Ai when the burst length is set to four and by A3-Ai
when the burst length is set to eight (where Ai is the
most significant column address bit for a given con-
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
* M13 and M12 (BA0 and BA1)
must be “0, 0” to select the
base mode register (vs. the
extended mode register).
Reserved states should not be used, as unknown
When a READ or WRITE command is issued, a
0*
13
BA1
0*
12
Mode Register Definition
BA0
11
A11
Operating Mode
10
A10
9
A9
M11
0
0
-
8
A8
M10
0
0
-
Figure 1
M6
7
A7 A6 A5 A4 A3
0
0
0
0
1
1
1
1
CAS Latency BT
M9
0
0
-
M5
6
0
0
1
1
0
0
1
1
M8
M4
0
1
5
-
0
1
0
1
0
1
0
1
M7
4
0
0
-
M3
0
1
M6-M0
3
Valid
Valid
M2
Burst Length
CAS Latency
-
0
0
0
0
1
1
1
1
2
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
A2 A1 A0
M1
0
0
1
1
0
0
1
1
2.5
2
Operating Mode
Normal Operation
Normal Operation/Reset DLL
All other states reserved
1
M0
0
1
0
1
0
1
0
1
0
Burst Type
Interleaved
Sequential
Reserved
Reserved
Reserved
Reserved
Reserved
M3 = 0
Mode Register (Mx)
Address Bus
2
4
8
Burst Length
Reserved
Reserved
Reserved
Reserved
Reserved
M3 = 1
2
4
8
10
figuration). The remaining (least significant) address
bit(s) is (are) used to select the starting location within
the block. The programmed burst length applies to
both READ and WRITE bursts.
Burst Type
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
mined by the burst length, the burst type and the
starting column address, as shown in Table 1.
NOTE: 1. For a burst length of two, A1-Ai select the two-
Length
Burst
Accesses within a given burst may be programmed
The ordering of accesses within a burst is deter-
2
4
8
2. For a burst length of four, A2-Ai select the four-
3. For a burst length of eight, A3-Ai select the eight-
4. Whenever a boundary of the block is reached
Micron Technology, Inc., reserves the right to change products or specifications without notice.
data-element block; A0 selects the first access
within the block.
data-element block; A0-A1 select the first access
within the block.
data-element block; A0-A2 select the first access
within the block.
within a given sequence above, the following
access wraps within the block.
Starting Column
A2 A1 A0
0
0
0
0
1
1
1
1
Address
A1 A0
BURST DEFINITION
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
128Mb: x4, x8, x16
TABLE 1
Type = Sequential
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
Order of Accesses Within a Burst
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1
1-0
DDR SDRAM
PRELIMINARY
©2001, Micron Technology, Inc.
Type = Interleaved
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1
1-0