MT46V16M8TG-8L MICRON [Micron Technology], MT46V16M8TG-8L Datasheet - Page 16

• Manufacturer Part Number: MT46V16M8TG-8L
• Description: DOUBLE DATA RATE DDR SDRAM
• Manufacturer: MICRON [Micron Technology]

Operations
BANK/ROW ACTIVATION
issued to a bank within the DDR SDRAM, a row in that
bank must be “opened.” This is accomplished via the
ACTIVE command, which selects both the bank and
the row to be activated, as shown in Figure 4.
a READ or WRITE command may be issued to that
row, subject to the
should be divided by the clock period and rounded up
to the next whole number to determine the earliest
clock edge after the ACTIVE command on which a
READ or WRITE command can be entered. For ex-
ample, a
clock (7.5ns period) results in 2.7 clocks rounded to 3.
This is reflected in Figure 5, which covers any case where
2 <
case for
other specification limits from time units to clock
cycles).
in the same bank can only be issued after the previous
active row has been “closed” (precharged). The mini-
mum time interval between successive ACTIVE com-
mands to the same bank is defined by
can be issued while the first bank is being accessed,
which results in a reduction of total row-access over-
head. The minimum time interval between successive
ACTIVE commands to different banks is defined by
t
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
COMMAND
RRD.
BA0, BA1
Before any READ or WRITE commands can be
After a row is opened with an ACTIVE command,
A subsequent ACTIVE command to a different row
A subsequent ACTIVE command to another bank
t
A0-A11
RCD (MIN)/
CK#
CK
t
RCD; the same procedure is used to convert
t
Example: Meeting
RCD specification of 20ns with a 133 MHz
Bank x
Row
ACT
T0
t
CK ≤ 3. (Figure 5 also shows the same
t
RCD specification.
NOP
T1
t RRD
t
RCD (
t
RC.
t
RCD (MIN)
NOP
T2
t
RRD) MIN When 2 <
Figure 5
Bank y
Row
16
ACT
T3
Activating a Specific Row in
NOP
T4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
A0-A11
t
RCD (
BA0,1
RAS#
CAS#
WE#
CKE
CK#
CS#
t RCD
CK
a Specific Bank
t
RRD) MIN/
128Mb: x4, x8, x16
Figure 4
HIGH
RA = Row Address
BA = Bank Address
T5
NOP
BA
RA
DDR SDRAM
t
RD/WR
CK < 3
PRELIMINARY
Bank y
T6
Col
©2001, Micron Technology, Inc.
DON’T CARE
T7
NOP