MT46V16M8TG-8L MICRON [Micron Technology], MT46V16M8TG-8L Datasheet - Page 37

• Manufacturer Part Number: MT46V16M8TG-8L
• Description: DOUBLE DATA RATE DDR SDRAM
• Manufacturer: MICRON [Micron Technology]

PRECHARGE
deactivate the open row in a particular bank or the
open row in all banks. The bank(s) will be available for
a subsequent row access some specified time (
the PRECHARGE command is issued. Input A10 deter-
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
The PRECHARGE command (Figure 25) is used to
A0-A9, A11
BA = Bank Address (if A10 is LOW;
otherwise “Don’t Care”)
PRECHARGE Command
BA0,1
CAS#
COMMAND
RAS#
WE#
A10
CKE
CK#
CS#
CK
CKE
CK#
CK
No READ/WRITE
access in progress
Figure 25
HIGH
VALID
ALL BANKS
ONE BANK
T0
BA
t
IS
NOP
T1
Enter power-down mode
t
RP) after
Power-Down
Figure 26
T2
(
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(
)
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(
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(
(
(
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)
37
mines whether one or all banks are to be precharged,
and in the case where only one bank is to be precharged,
inputs BA0, BA1 select the bank. When all banks are to
be precharged, inputs BA0, BA1 are treated as “Don’t
Care.” Once a bank has been precharged, it is in the idle
state and must be activated prior to any READ or
WRITE commands being issued to that bank.
POWER-DOWN (CKE Not Active)
be active at all times an access is in progress: from the
issuing of a READ or WRITE command until comple-
tion of the burst. Thus a clock suspend is not sup-
ported. For READs, a burst completion is defined when
the Read Postamble is satisfied; For WRITEs, a burst
completion is defined when the Write Postamble is
satisfied.
registered LOW. If power-down occurs when all banks
are idle, this mode is referred to as precharge power-
down; if power-down occurs when there is a row active
in any bank, this mode is referred to as active power-
down. Entering power-down deactivates the input
and output buffers, excluding CK, CK#, and CKE.
For maximum power savings, the DLL is frozen during
a precharge power-down. Exiting power-down re-
quires the device to be at the same voltage and fre-
quency as when it entered power-down. However,
power-down duration is limited by the refresh require-
ments of the device (
signal must be maintained at the inputs of the DDR
SDRAM, while all other input signals are “Don’t Care.”
CKE is registered HIGH (in conjunction with a NOP or
DESELECT command). A valid executable command
may be applied one clock cycle later.
Ta0
Unlike SDR SDRAMs, DDR SDRAMs require CKE to
Power-down (Figure 26) is entered when CKE is
While in power-down, CKE LOW and a stable clock
The power-down state is synchronously exited when
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
IS
Ta1
NOP
Exit power-down mode
128Mb: x4, x8, x16
t
REFC).
VALID
Ta2
DON’T CARE
DDR SDRAM
PRELIMINARY
©2001, Micron Technology, Inc.