MT46V16M8TG-8L MICRON [Micron Technology], MT46V16M8TG-8L Datasheet - Page 57

• Manufacturer Part Number: MT46V16M8TG-8L
• Description: DOUBLE DATA RATE DDR SDRAM
• Manufacturer: MICRON [Micron Technology]

128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
DQ8 - DQ15 and UDQS, collectively
DQ0 - DQ7 and LDQS, collectively
NOTE: 1. DQs transitioning after DQS transition define t DQSQ
DQ (First data no longer valid)
DQ (First data no longer valid)
DQ (First data no longer valid)
DQ (First data no longer valid)
2. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7.
3. t DQSQ is derived at each DQS clock edge and is not
window. LDQS defines the lower byte and
UDQS defines the upper byte.
cumulative over time and begins with DQS transition
and ends with the last valid transition of DQs .
DQ (Last data valid)
DQ (Last data valid)
DQ (Last data valid)
DQ (Last data valid)
Data Output Timing –
UDQS
LDQS
CK#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CK
1
1
2
2
2
2
2
2
2
7
7
7
7
7
7
7
2
7
2
2
7
7
6
6
T1
t HP
5
Figure 29A - x16
t
t HP
DQSQ,
5
t DQSQ
t QH
t DQSQ
T2
t QH
4
Data Valid
3
57
window
Data Valid
4
T2
T2
T2
window
t HP
3
t
QH and Data Valid Window
T2
T2
T2
5
4. t QH is derived from t HP: t QH = t HP - t QHS.
5. t HP is the lesser of t CL or t CH clock transition
6. The data valid window is derived for each
7. DQ8, DQ9, DQ10, D11, DQ12, DQ13, DQ14, or DQ15.
t DQSQ
collectively when a bank is active.
DQS transition and is t QH minus t DQSQ.
T2n
t QH
t DQSQ
Data Valid
t QH
4
window
3
t HP
T2n
Data Valid
T2n
T2n
4
window
3
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T2n
T2n
T2n
T3
t DQSQ
t QH
t DQSQ
t QH
4
t HP
Data Valid
3
window
Data Valid
5
4
window
T3
T3
T3
3
T3
128Mb: x4, x8, x16
T3
T3
T3n
t DQSQ
t DQSQ
t HP
t QH
t QH
Data Valid
5
4
4
Data Valid
window
3
3
window
T3n
T3n
T4
T3n
T3n
T3n
T3n
DDR SDRAM
PRELIMINARY
©2001, Micron Technology, Inc.