MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 653

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Command Sequence:
Operand Data:
Result Data:
30.5.3.3.11 Read Debug Module Register (
Read the selected debug module register and return the 32-bit result. The only valid register selection for
the
BKPT]; as well as the trigger status bits (CSR[BSTAT]) if either a level-2 breakpoint has been triggered
or a level-1 breakpoint has been triggered and no level-2 breakpoint has been enabled.
Command/Result Formats:
Table 30-20
Freescale Semiconductor
RDMREG
Command
0x01–0x1F
DRc[4:0]
WCREG
0x00
???
Result
command is CSR (DRc = 0x00). Note that this read of the CSR clears CSR[FOF, TRG, HALT,
shows the definition of DRc encoding.
15
’NOT READY’
MS ADDR
This instruction requires two longword operands. The first selects the register to
which the operand data is to be written; the second contains the data.
Successful write operations return 0xFFFF. Bus errors on the write cycle are
indicated by the setting of bit 16 in the status message and by a data pattern of
0x0001.
0x2
Debug Register Definition
Configuration/Status
Figure 30-37.
Table 30-20. Definition of DRc Encoding—Read
Figure 30-36.
Reserved
12
’NOT READY’
MS ADDR
11
RDMREG
WCREG
0xD
RDMREG
Command/Result Formats
Command Sequence
’NOT READY’
D[31:16]
MS DATA
8
D[15:0]
’NOT READY’
LS DATA
Mnemonic
)
7
CSR
—
100
5
REGISTER
CONTROL
WRITE
Initial State
4
0x0
—
’CMD COMPLETE’
’NOT READY’
DRc
NEXT CMD
BERR
XXX
XXX
’NOT READY’
NEXT CMD
p. 30-10
Page
Debug Support
—
0
30-35