MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 300

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

DMA Controller Module
16.3
The DMA module can transfer data faster than the ColdFire core. The term “direct memory access” refers
to a fast method of moving data within system memory (including memory and peripheral devices) with
minimal processor intervention, greatly improving overall system performance. The DMA module
consists of four independent, functionally equivalent channels, so references to DMA in this chapter apply
to any of the channels. It is not possible to implicitly address all four channels at once.
The processor generates DMA requests internally by setting DCR[START]; the UART modules and DMA
timers can generate a DMA request by asserting internal DREQ signals. The processor can program bus
bandwidth for each channel. The channels support cycle-steal and continuous transfer modes; see
Section 16.5.1, “Transfer Requests (Cycle-Steal and Continuous
The DMA controller supports dual-address transfers. The DMA channels support up to 32 data bits.
Any operation involving the DMA module follows the same three steps:
16.4
This section describes each internal register and its bit assignment. Note that modifying DMA control
registers during a DMA transfer can result in undefined operation.
controller registers. Note the differences for the byte count registers depending on the value of
MPARK[BCR24BIT]. See
16-4
•
1. Channel initialization—Channel registers are loaded with control information, address pointers,
2. Data transfer—The DMA accepts requests for operand transfers and provides addressing and bus
3. Channel termination—Occurs after the operation is finished, either successfully or due to an error.
Dual-address transfers—A dual-address transfer consists of a read followed by a write and is
initiated by an internal request using the START bit or by asserting DREQ. Two types of transfer
can occur: a read from a source device or a write to a destination device. See
information.
and a byte-transfer count.
control for the transfers.
The channel indicates the operation status in the channel’s DSR, described in
“DMA Status Registers
DMA Transfer Overview
DMA Controller Module Programming Model
Section 8.5.3, “Bus Master Park Register
(DSR0–DSR3).”
DMA
DMA
Figure 16-3. Dual-Address Transfer
Control and Data
Control and Data
Peripheral
Peripheral
Memory/
Memory/
Modes).”
Table 16-2
(MPARK)” for further information.
shows the mapping of DMA
Figure 16-3
Freescale Semiconductor
Section 16.4.5,
for more