MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 439
MCF5282CVM66
Manufacturer Part Number
MCF5282CVM66
Description
Manufacturer
Freescale
Datasheet
1.MCF5282CVM66.pdf
(766 pages)
Specifications of MCF5282CVM66
Cpu Family
MCF528x
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
66MHz
Interface Type
CAN/I2C/QSPI/UART
Total Internal Ram Size
64KB
# I/os (max)
150
Number Of Timers - General Purpose
12
Operating Supply Voltage (typ)
3.3V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
256
Package Type
MA-BGA
Program Memory Type
Flash
Program Memory Size
512KB
Lead Free Status / RoHS Status
Compliant
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UART Modules
optional parity bit, and the programmed number of stop bits. The lsb is sent first. Data is shifted from the
transmitter output on the falling edge of the clock source.
After the stop bits are sent, if no new character is in the transmitter holding register, the UTXDn output
remains high (mark condition) and the transmitter empty bit (USRn[TXEMP]) is set. Transmission
resumes and TXEMP is cleared when the CPU loads a new character into the UART transmit buffer
(UTBn). If the transmitter receives a disable command, it continues until any character in the transmitter
shift register is completely sent.
If the transmitter is reset through a software command, operation stops immediately (see
Section 23.3.5,
“UART Command Registers
(UCRn)”). The transmitter is reenabled through the UCRn to resume
operation after a disable or software reset.
If the clear-to-send operation is enabled, UCTSn must be asserted for the character to be transmitted. If
UCTSn is negated in the middle of a transmission, the character in the shift register is sent and UTXDn
remains in mark state until UCTSn is reasserted. If transmitter is forced to send a continuous low condition
by issuing a
command, transmitter ignores the state of UCTSn.
SEND BREAK
If the transmitter is programmed to automatically negate URTSn when a message transmission completes,
URTSn must be asserted manually before a message is sent. In applications in which the transmitter is
disabled after transmission is complete and URTSn is appropriately programmed, URTSn is negated one
bit time after the character in the shift register is completely transmitted. The transmitter must be manually
reenabled by reasserting URTSn before the next message is sent.
Figure 23-19
shows the functional timing information for the transmitter.
Freescale Semiconductor
23-19
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