MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 197

MCF5282CVM66

Manufacturer Part Number
MCF5282CVM66
Description
Manufacturer
Freescale
Datasheet

Specifications of MCF5282CVM66

Cpu Family
MCF528x
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
66MHz
Interface Type
CAN/I2C/QSPI/UART
Total Internal Ram Size
64KB
# I/os (max)
150
Number Of Timers - General Purpose
12
Operating Supply Voltage (typ)
3.3V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
256
Package Type
MA-BGA
Program Memory Type
Flash
Program Memory Size
512KB
Lead Free Status / RoHS Status
Compliant

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10.3.2
The IMRHn and IMRLn registers are each 32 bits in size and provide a bit map for each interrupt to allow
the request to be disabled (1 = disable the request, 0 = enable the request). The IMRn is set to all ones by
reset, disabling all interrupt requests. The IMRn can be read and written. A write that sets bit 0 of the IMR
forces the other 63 bits to be set, disabling all interrupt sources, and providing a global mask-all capability.
Freescale Semiconductor
.
31–0
31–1
Bits
Bits
0
Reset
Reset
Field
Field
R/W
R/W
Interrupt Mask Register (IMRHn, IMRLn)
Name
Name
INT
INT
31
15
Interrupt pending. Each bit corresponds to an interrupt source. The corresponding IMRHn bit
determines whether an interrupt condition can generate an interrupt. At every system clock, the
IPRHn samples the signal generated by the interrupting source. The corresponding IPRHn bit
reflects the state of the interrupt signal even if the corresponding IMRHn bit is set.
0 The corresponding interrupt source does not have an interrupt pending
1 The corresponding interrupt source has an interrupt pending
Interrupt Pending. Each bit corresponds to an interrupt source. The corresponding IMRLn bit
determines whether an interrupt condition can generate an interrupt. At every system clock, the
IPRLn samples the signal generated by the interrupting source. The corresponding IPRLn bit
reflects the state of the interrupt signal even if the corresponding IMRLn bit is set.
0 The corresponding interrupt source does not have an interrupt pending
1 The corresponding interrupt source has an interrupt pending
Reserved, should be cleared.
Figure 10-2. Interrupt Pending Register Low (IPRLn)
Table 10-4. IPRHn Field Descriptions
Table 10-5. IPRLn Field Descriptions
IPSBAR + 0xC04, 0xD04
0000_0000_0000_0000
0000_0000_0000_0000
INT[16:1]
INT[31:16]
Description
Description
R
R
Interrupt Controller Modules
1
16
0
10-7

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