MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 427

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Freescale Semiconductor
TXRTS
TXCTS
Field
7–6
3–0
CM
SB
5
4
Channel mode. Selects a channel mode.
00 Normal
01 Automatic echo
10 Local loopback
11 Remote loopback
Transmitter ready-to-send. Controls negation of URTSn to automatically terminate a message transmission.
Attempting to program a receiver and transmitter in the same UART for URTSn control is not permitted and disables
URTSn control for both.
0 The transmitter has no effect on URTSn.
1 In applications where the transmitter is disabled after transmission completes, setting this bit automatically clears
Transmitter clear-to-send. If TXCTS and TXRTS are set, TXCTS controls the operation of the transmitter.
0 UCTSn has no effect on the transmitter.
1 Enables clear-to-send operation. The transmitter checks the state of UCTSn each time it is ready to send a
Stop-bit length control. Selects length of stop bit appended to the transmitted character. Stop-bit lengths of 9/16 to
2 bits are programmable for 6–8 bit characters. Lengths of 1-1/16 to 2 bits are programmable for 5-bit characters. In
all cases, the receiver checks only for a high condition at the center of the first stop-bit position, one bit time after the
last data bit or after the parity bit, if parity is enabled. If an external 1x clock is used for the transmitter, clearing bit 3
selects one stop bit and setting bit 3 selects two stop bits for transmission.
UOP[RTS] one bit time after any characters in the transmitter shift and holding registers are completely sent,
including the programmed number of stop bits.
character. If UCTSn is asserted, the character is sent; if it is deasserted, the signal UTXDn remains in the high
state and transmission is delayed until UCTSn is asserted. Changes in UCTSn as a character is being sent do
not affect its transmission.
Table 23-4. UMR2n Field Descriptions
0000
0001
0010
0011
0100
0101
0110
0111
SB
Section 23.4.3, “Looping
5 Bits
1.063
1.125
1.188
1.250
1.313
1.375
1.438
1.500
Description
6–8 Bits
0.563
0.625
0.688
0.750
0.813
0.875
0.938
1.000
Modes,” describes individual modes.
1000
1001
1010
1011
1100
1101
1110
1111
SB
5–8 Bits
1.563
1.625
1.688
1.750
1.813
1.875
1.938
2.000
UART Modules
23-7