MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 483

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

25.4.8.1 Configuring the FlexCAN Bit Timing
The following considerations must be observed when programming bit timing functions.
25.4.9
There are two error counters in the FlexCAN: transmit error counter (TXECTR), and receive error counter
(RXCTR). The rules for increasing and decreasing these counters are described in the CAN protocol, and
are fully implemented in the FlexCAN. Each counter comprises the following:
Both counters are read only (except for Test/Freeze/Halt modes).
Freescale Semiconductor
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System Clock
Freq (Mhz)
If the programmed PRESDIV value results in a single system clock per one time quantum, then the
PSEG2 field in CANCTRL1 register should not be programmed to zero.
If the programmed PRESDIV value results in a single system clock per one time quantum, then the
information processing time (IPT) equals three time quanta, otherwise it equals two time quanta.
If PSEG2 equals two, then the FlexCAN transmits one time quantum late relative to the scheduled
sync segment.
If the prescaler and bit timing control fields are programmed to values that result in fewer than ten
system clock periods per CAN bit time and the CAN bus loading is 100%, anytime the rising edge
of a start-of-frame (SOF) symbol transmitted by another node occurs during the third bit of the
intermission between messages, the FlexCAN may not be able to prepare a message buffer for
transmission in time to begin its own transmission and arbitrate against the message which
transmitted the early SOF.
The FlexCAN bit time must be programmed to be greater than or equal to nine system clocks, or
correct operation is not guaranteed.
8 bit up/down counter
Increment by 8 (Rx_Err_Counter also by 1)
Decrement by 1
Avoid decrement when equal to zero
Rx_Err_Counter preset to a value 119 ≤ x ≤ 127
Value after reset = zero
Detect values for Error Passive, Bus Off and Error Active transitions and for alerting the host.
48
40
32
48
40
32
FlexCAN Error Counters
Can bit-rate
Table 25-7. Examples of System Clock/CAN Bit-Rate/S-Clock
(Mhz)
0.125
0.125
0.125
1
1
1
S-Clock Freq
Possible
1,1.5,2,3
8,12,24
1,2,2.5
(Mhz)
10,20
8,16
1,2
time-quanta/bit
number of
8,12,16,24
Possible
8,12,24
8,16,20
10,20
8,16
8,16
programed
Pre-Scaler
24,16,12,8
value + 1
20,10,8
3,2,1
16,8
2,1
2,1
Max 25 time-quanta
Min 8 time-quanta
Comments
FlexCAN
25-13