MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 425

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

23.3.1
The UMR1n registers control UART module configuration. UMR1n can be read or written when the mode
register pointer points to it, at RESET or after a
UCRn[MISC]. After UMR1n is read or written, the pointer points to UMR2n.
Freescale Semiconductor
RXRTS
RXIRQ/
FFULL
Field
ERR
4–3
PM
7
6
5
IPSBAR
Offset:
Reset:
Receiver request-to-send. Allows the URTSn output to control the UCTSn input of the transmitting device to prevent
receiver overrun. If the receiver and transmitter are incorrectly programmed for URTSn control, URTSn control is
disabled for both. Transmitter RTS control is configured in UMR2n[TXRTS].
0 The receiver has no effect on URTSn.
1 When a valid start bit is received, URTSn is negated if the UART's FIFO is full. URTSn is reasserted when the
Receiver interrupt select.
0 RXRDY is the source generating interrupt or DMA requests.
1 FFULL is the source generating interrupt or DMA requests.
Error mode. Configures the FIFO status bits, USRn[RB,FE,PE].
0 Character mode. The USRn values reflect the status of the character at the top of the FIFO. ERR must be 0 for
1 Block mode. The USRn values are the logical OR of the status for all characters reaching the top of the FIFO since
Parity mode. Selects the parity or multidrop mode for the UART. The parity bit is added to the transmitted character,
and the receiver performs a parity check on incoming data. The value of PM affects PT, as shown below.
W
R
FIFO has an empty position available.
correct A/D flag information when in multidrop mode.
the last
Registers
UART Mode Registers 1 (UMR1n)
0x00_0200 (UMR10)
0x00_0240 (UMR11)
0x00_0280 (UMR12)
1
RXRTS
After UMR1n is read or written, the pointer points to UMR2n
0
7
RESET ERROR STATUS
(UCRn).”
RXIRQ/
FFULL
0
6
Figure 23-3. UART Mode Registers 1 (UMR1n)
Table 23-3. UMR1n Field Descriptions
command for the UART was issued. See
ERR
0
5
RESET MODE REGISTER POINTER
0
4
Description
PM
0
3
Section 23.3.5, “UART Command
PT
0
2
command using
Access: User read/write
1
0
B/C
UART Modules
0
0
1
23-5