MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 333

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

R_BOUND
17.4.21 FIFO Receive Start Register (FRSR)
FRSR indicates the starting address of the receive FIFO. FRSR marks the boundary between the transmit
and receive FIFOs. The transmit FIFO uses addresses from the start of the FIFO to the location four bytes
before the address programmed into the FRSR. The receive FIFO uses addresses from FRSR to FRBR
inclusive.
Hardware initializes the FRSR register at reset. FRSR only needs to be written to change the default value.
17.4.22 Receive Descriptor Ring Start Register (ERDSR)
ERDSR points to the start of the circular receive buffer descriptor queue in external memory. This pointer
must be 32-bit aligned; however, it is recommended it be made 128-bit aligned (evenly divisible by 16).
This register is not reset and must be initialized prior to operation.
Freescale Semiconductor
R_FSTART
31–10
Field
9–2
1–0
31–11
Field
9–2
1–0
10
IPSBAR
Offset:
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0
Reserved, read as 0 (except bit 10, which is read as 1).
Read-only. Highest valid FIFO RAM address.
Reserved, read as 0.
W
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Reserved, must be cleared.
Reserved, must be set.
Address of first receive FIFO location. Acts as delimiter between receive and transmit FIFOs. For proper
operation, ensure that R_FSTART is set to 0x48 or greater.
Reserved, must be cleared.
0x1150
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Figure 17-21. FIFO Receive Start Register (FRSR)
Table 17-24. FRBR Field Descriptions
Table 17-25. FRSR Field Descriptions
Description
Description
8
R_FSTART
7
Access: User read/write
Fast Ethernet Controller (FEC)
6
5
4
3
2
0
1
0
0
0
17-23