MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 156

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

System Control Module (SCM)
The physical base address programmed in both copies of the RAMBAR is typically the same value;
however, they can be programmed to different values. By definition, the base address must be a
0-modulo-size value.
The SRAM modules are configured through the RAMBAR shown in
For details on the processor's view of the local SRAM memories, see
Register
8-4
•
•
•
31–16
15–10
Bits
Address
8–0
9
RAMBAR specifies the base address of the SRAM.
All undefined bits are reserved. These bits are ignored during writes to the RAMBAR and return
zeros when read.
The back door enable bit, RAMBAR[BDE], is cleared at reset, disabling the module access to the
SRAM.
Reset
Reset
Field BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16
Field
(RAMBAR).”
R/W
R/W
Name
BDE
BA
—
—
The RAMBAR default value of 0x0000_0000 is invalid. The RAMBAR
located in the processor’s CPU space must be initialized with the valid bit
set before the CPU (or modules) can access the on-chip SRAM (see
Chapter 5, “Static RAM
31
15
Base address. Defines the memory module's base address on a 64-Kbyte boundary corresponding
to the physical array location within the 4 Gbyte address space supported by ColdFire.
Reserved, should be cleared.
Back door enable. Qualifies the module accesses to the memory.
0 Disables module accesses to the memory.
1 Enables module accesses to the memory.
NOTE: The SPV bit in the CPU’s RAMBAR must also be set to allow dual port access to the SRAM.
For more information, see
Reserved, should be cleared.
30
Figure 8-2. Memory Base Address Register (RAMBAR)
29
—
28
Table 8-3. RAMBAR Field Description
27
(SRAM)” for more information.
Section 5.3.1, “SRAM Base Address Register
26
10
BDE
0000_0000_0000_0000
0000_0000_0000_0000
25
9
NOTE
IPSBAR + 0x008
24
8
R/W
R/W
Description
23
22
Section 5.3.1, “SRAM Base Address
21
Figure
—
20
8-2.
(RAMBAR).”
19
Freescale Semiconductor
18
17
16
0