MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 373

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

20.5.1
Freescale Semiconductor
1
2
S = CPU supervisor mode access only.
Writes have no effect, reads return 0s, and the access terminates without a transfer error exception.
Bit(s)
0x1A_001C
0x1A_001D
7–4
3–0
0x1A_001A
0x1A_001B
0x1A_001E
0x1A_001F
0x1A_0017
0x1A_0018
0x1A_0019
GPTA
GPT Input Capture/Output Compare Select Register (GPTIOS)
IPSBAR Offset
Address
Reset
Figure 20-2. GPT Input Capture/Output Compare Select Register (GPTIOS)
Field
R/W
Name
IOS
—
0x1B_001A
0x1B_001B
0x1B_001C
0x1B_001D
0x1B_001E
0x1B_001F
0x1B_0017
0x1B_0018
0x1B_0019
GPTB
7
Table 20-3. GPT Modules Memory Map (continued)
Reserved, should be cleared.
I/O select. The IOS[3:0] bits enable input capture or output compare operation for the
corresponding timer channels. These bits are read anytime (always read 0x00), write
anytime.
1 Output compare enabled
0 Input capture enabled
Table 20-4. GPTIOS Field Descriptions
—
Pulse Accumulator Counter Register High (GPTPACNTH)
Pulse Accumulator Counter Register Low (GPTPACNTL)
IPSBAR + 0x401A_0000, 0x401B_0000
Pulse Accumulator Control Register (GPTPACTL)
Pulse Accumulator Flag Register (GPTPAFLG)
GPT Port Data Direction Register (GPTDDR)
GPT Channel 3 Register Low (GPTC3L)
GPT Port Data Register (GPTPORT)
GPT Test Register (GPTTST)
0000_0000
4
R/W
Reserved
Bits 7–0
3
Description
General Purpose Timer Modules (GPTA and GPTB)
(2)
IOS
0
Access
—
S
S
S
S
S
S
S
S
1
20-5