MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 623

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Debug Support
target instruction. The PST can continue with the next instruction before the address has completely
displayed on DDATA because of the DDATA FIFO. If the FIFO is full and the next instruction has captured
values to display on DDATA, the pipeline stalls (PST = 0x0) until space is available in the FIFO.
30.4
Programming Model
In addition to the existing BDM commands that provide access to the processor’s registers and the memory
subsystem, the debug module contains 19 registers to support the required functionality. These registers
are also accessible from the processor’s supervisor programming model by executing the WDEBUG
instruction (write only). Thus, the breakpoint hardware in the debug module can be written by the external
development system using the debug serial interface or by the operating system running on the processor
core. Software is responsible for guaranteeing that accesses to these resources are serialized and logically
consistent. Hardware provides a locking mechanism in the CSR to allow the external development system
to disable any attempted writes by the processor to the breakpoint registers (setting CSR[IPW]). BDM
commands must not be issued if the device is using the WDEBUG instruction to access debug module
registers or the resulting behavior is undefined.
These registers, shown in
Figure
30-4, are treated as 32-bit quantities, regardless of the number of
implemented bits.
Freescale Semiconductor
30-5